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| m68hc08 microcontrollers freescale.com mc68hc908az60a mc68hc908as60a MC68HC908AZ60E data sheet mc68hc908az60a rev. 6 05/2006
mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2006. all rights reserved. mc68hc908az60a mc68hc908as60a data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 4 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 chapter 3 random-access memo ry (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 4 flash-1 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 5 flash-2 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 6 eeprom-1 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 chapter 7 eeprom-2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 8 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 9 system integr ation module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 10 clock generator m odule (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 chapter 11 configuration register (config-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 chapter 12 configuration register (config-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 chapter 13 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 chapter 14 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 chapter 15 computer operati ng properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 chapter 16 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 17 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 chapter 18 serial communications interf ace (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 chapter 19 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 20 timer interface module b (tim b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 chapter 21 programmable interr upt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chapter 22 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 chapter 23 mscan controller (mscan08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 list of chapters mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 6 freescale semiconductor chapter 24 keyboard module ( kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 chapter 25 timer interface module a (tim a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 chapter 26 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 chapter 27 byte data link cont roller (bdlc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 chapter 28 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 appendix a mc68hc908as60 and mc68hc908az60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 appendix b MC68HC908AZ60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.5 analog power supply pin (v dda ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.7 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.8 adc analog power supply pin (v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.9 adc analog ground pin (a vss/ v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.10 adc reference high voltage pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.11 port a input/output (i/o) pins (pta7?pta0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.12 port b i/o pins (ptb7/atd7?ptb0/atd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.13 port c i/o pins (ptc5?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.14 port d i/o pins (ptd7?ptd0/atd8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.15 port e i/o pins (pte7/spsck?pte0/txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.16 port f i/o pins (ptf6?ptf0/tach2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.17 port g i/o pins (ptg2/kbd2?ptg0/kbd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.18 port h i/o pins (pth1/kbd4?pth0/kbd3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.19 can transmit pin (cantx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.20 can receive pin (canrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.21 bdlc transmit pin (bdtxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4.22 bdlc receive pin (bdrxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 2 memory map 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 additional status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4 vector addresses and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 3 random-access memory (ram) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 8 freescale semiconductor chapter 4 flash-1 memory 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3 flash-1 control and block protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.1 flash-1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.2 flash-1 block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4.4 flash-1 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5 flash-1 mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6 flash-1 page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.7 flash-1 program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 chapter 5 flash-2 memory 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3 flash-2 control and block protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.1 flash-2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.2 flash-2 block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 5.4 flash-2 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.5 flash-2 mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.6 flash-2 page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7 flash-2 program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 chapter 6 eeprom-1 memory 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3 eeprom-1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.1 eeprom-1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.2 eeprom-1 timebase requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.3 eeprom-1 program/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.4.4 eeprom-1 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 6.4.5 eeprom-1 programming and erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.5.1 program/erase using auto bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.4.5.2 eeprom-1 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.4.5.3 eeprom-1 erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5 eeprom-1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.5.1 eeprom-1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 6.5.2 eeprom-1 array configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 9 6.5.3 eeprom-1 nonvolatile register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5.4 eeprom-1 timebase divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5.5 eeprom-1 timebase divider nonvolat ile register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 7 eeprom-2 memory 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3 eeprom-2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.1 eeprom-2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.2 eeprom-2 timebase requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.4.3 eeprom-2 program/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.4 eeprom-2 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 7.4.5 eeprom-2 programming and erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.5.1 program/erase using auto bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.5.2 eeprom-2 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.5.3 eeprom-2 erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.5 eeprom-2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 eeprom-2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 7.5.2 eeprom-2 array configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5.3 eeprom-2 nonvolatile register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.5.4 eeprom-2 timebase divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.5.5 eeprom-2 timebase divider nonvolat ile register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 8 central processor unit (cpu) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 10 freescale semiconductor chapter 9 system integrati on module (sim) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.3.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 9.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5 program exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 chapter 10 clock generator module (cgm) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.3.1 crystal oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.3.2 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.3.2.1 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.3.2.2 acquisition and tracking modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.3.2.3 manual and automatic pll bandwidth modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.3.2.4 programming the pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.3.2.5 special programming exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.3.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.3.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 11 10.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 10.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.4 analog power pin (v dda ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.6 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.5.2 pll bandwidth control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 10.5.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.8 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.9 acquisition/lock time specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.9.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 40 10.9.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.9.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.9.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 chapter 11 configuration register (config-1) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 chapter 12 configuration register (config-2) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 chapter 13 break module (brk) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.3.1 flag protection during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.3.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.3.3 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.3.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.5 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 13.5.1 break status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 13.5.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 12 freescale semiconductor chapter 14 monitor rom (mon) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.3.1 entering monitor mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.3.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.3.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.3.4 break signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.3.5 commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3.6 mc68hc908as60a baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.3.7 mc68hc908az60a baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3.8 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 chapter 15 computer operatin g properly (cop) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.3.7 copd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.3.8 copl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.8 cop module during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 chapter 16 low-voltage inhibit (lvi) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.3 false reset protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 13 chapter 17 external interrupt module (irq) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 chapter 18 serial communications interface (sci) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 18.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 18.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 18.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 18.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 18.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 18.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 18.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 18.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 18.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 18.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 18.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 18.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.6 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.7.1 pte0/sctxd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 18.7.2 pte1/scrxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.8.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.8.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 18.8.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.8.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.8.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.8.7 sci baud rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 14 freescale semiconductor chapter 19 serial peripheral interface (spi) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.3 pin name and register name conventi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 19.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 19.4.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 19.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.5.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 19.5.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.5.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.5.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19.8 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 19.9 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.11 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 19.12 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.12.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.12.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.12.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 19.12.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 19.12.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.13 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.13.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19.13.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 19.13.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 chapter 20 timer interface module b (timb) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 20.3.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 20.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 20.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 20.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 20.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 30 20.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 20.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 15 20.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.6 timb during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 20.7.1 timb clock pin (ptd4/atd12/tbclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 20.7.2 timb channel i/o pins (ptf5/tbch1?ptf4/tbch0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 20.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 20.8.1 timb status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 20.8.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 20.8.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 20.8.4 timb channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 20.8.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 chapter 21 programmable interrupt timer (pit) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 21.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 21.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 21.4 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 21.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 21.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 21.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 21.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 21.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 21.7.1 pit status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 45 21.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 21.7.3 pit counter modulo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 48 chapter 22 input/output ports 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 22.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 22.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 22.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 22.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 22.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 22.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 22.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 22.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 22.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 22.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 22.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 22.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 22.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 22.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 22.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 16 freescale semiconductor 22.7 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 22.7.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 22.7.2 data direction register f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 22.8 port g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 22.8.1 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 22.8.2 data direction register g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 22.9 port h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 22.9.1 port h data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 22.9.2 data direction register h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 chapter 23 mscan controll er (mscan08) 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 23.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 23.3 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 23.4 message storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 23.4.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 23.4.2 receive structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 23.4.3 transmit structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 23.5 identifier acceptance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 23.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23.6.1 interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23.6.2 interrupt vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 23.7 protocol violation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 23.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 23.8.1 mscan08 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 23.8.2 mscan08 soft reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 23.8.3 mscan08 power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 23.8.4 cpu wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 23.8.5 programmable wakeup function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 23.9 timer link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 23.10 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 23.11 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 23.12 programmer?s model of message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 23.12.1 message buffer outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 23.12.2 identifier registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 23.12.3 data length register (dlr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 23.12.4 data segment registers (dsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23.12.5 transmit buffer priority registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23.13 programmer?s model of control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 23.13.1 mscan08 module control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 23.13.2 mscan08 module control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 23.13.3 mscan08 bus timing register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 23.13.4 mscan08 bus timing register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 23.13.5 mscan08 receiver flag register (crflg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 23.13.6 mscan08 receiver interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 23.13.7 mscan08 transmitter flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 17 23.13.8 mscan08 transmitter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 23.13.9 mscan08 identifier acceptance control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 23.13.10 mscan08 receive error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 23.13.11 mscan08 transmit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 23.13.12 mscan08 identifier acceptance registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 23.13.13 mscan08 identifier mask registers (cidmr0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 chapter 24 keyboard module (kbi) 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 24.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 24.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 24.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 24.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 24.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 24.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 24.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 24.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 24.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 24.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 chapter 25 timer interface module a (tima) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 25.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 25.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 25.3.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 25.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 25.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 25.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 25.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 11 25.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 25.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 25.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 25.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 25.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 25.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 25.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 25.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 25.6 tima during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 25.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 25.7.1 tima clock pin (ptd6/atd14/taclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 25.7.2 tima channel i/o pins (ptf3?ptf0/tach2 and pte3/tach1?pte2/tach0) . . . . . . . 316 25.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 25.8.1 tima status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 25.8.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 25.8.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 25.8.4 tima channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 25.8.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 18 freescale semiconductor chapter 26 analog-to-digital converter (adc) 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 26.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 26.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 26.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 26.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 26.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 26.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 26.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 26.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 26.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.6.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) . . . . . . . . . . . . . 330 26.6.2 adc analog ground pin (v ssa )/adc voltage reference low pin (v refl) . . . . . . . . . . . . 330 26.6.3 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 26.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 26.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 26.7.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 chapter 27 byte data link c ontroller (bdlc) 27.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 27.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 27.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 27.3.1 bdlc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 27.3.1.1 power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 27.3.1.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 27.3.1.3 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 27.3.1.4 bdlc wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 27.3.1.5 bdlc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 27.3.1.6 digital loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 27.3.1.7 analog loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 27.4 bdlc mux interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 27.4.1 rx digital filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 27.4.1.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 27.4.1.2 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 27.4.2 j1850 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 27.4.3 j1850 vpw symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 27.4.4 j1850 vpw valid/invalid bits and symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 27.4.5 message arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 27.5 bdlc protocol handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 27.5.1 protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 27.5.2 rx and tx shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 27.5.3 rx and tx shadow registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 50 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 19 27.5.4 digital loopback multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5.1 4x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5.2 receiving a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5.3 transmitting a message in block mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5.4 j1850 bus errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 27.5.5.5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 27.6 bdlc cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 27.6.1 bdlc analog and roundtrip delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 27.6.2 bdlc control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 27.6.3 bdlc control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 27.6.4 bdlc state vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 27.6.5 bdlc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 27.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 27.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 27.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 chapter 28 electrical specifications 28.1 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 28.1.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 28.1.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 28.1.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 28.1.4 5.0 volt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 28.1.5 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 28.1.6 adc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 28.1.7 5.0 vdc 0.5 v serial peripheral interface (spi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . 369 28.1.8 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 28.1.9 cgm component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 28.1.10 cgm acquisition/lock time information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 28.1.11 timer module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 28.1.12 ram memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 74 28.1.13 eeprom memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 28.1.14 flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 28.1.15 bdlc transmitter vpw symbol timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 28.1.16 bdlc receiver vpw symbol timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 28.1.17 bdlc transmitter dc electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 28.1.18 bdlc receiver dc electr ical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 28.2 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 28.2.1 51-pin plastic leaded chip carrier (plcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 28.2.2 64-pin quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 79 table of contents mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 20 freescale semiconductor appendix a mc68hc908as60 and mc68hc908az60 a.1 changes from the mc68hc908as60 and mc68hc908a z60 (non-a suffix devices) . . . . . . . 381 a.1.1 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 a.1.2 flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 a.1.2.1 flash architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 a.1.2.2 flash control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 81 a.1.2.3 flash programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 a.1.2.4 flash programming time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 a.1.2.5 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.2.6 flash endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.3 eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.3.1 eeprom architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.3.2 eeprom clock source and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.3.3 eeprom auto programming & erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 a.1.4 config-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 a.1.5 keyboard interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 a.1.6 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 a.1.7 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 a.1.8 monitor mode entry and cop disable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 a.1.9 low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 appendix b MC68HC908AZ60E b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 b.2 detailed memory map changes (mc68hc908as60 a references have been removed) . . . . 387 b.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 b.4 additional status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 b.5 vector addresses and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 b.6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 b.6.1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 b.7 configuration register (config-3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 98 b.8 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 b.9 mscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 b.10 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 revision history revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 glossary glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 21 chapter 1 general description 1.1 introduction the mc68hc908as60a, mc68hc908az60a, and mc68 hc908az60e are members of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and ar e available with a vari ety of modules, memory sizes and types, and package types. these parts are designed to emulate the mc68hc 08asxx and mc68hc08azxx automotive families and may offer extra features which are not available on thos e devices. it is the user?s responsibility to ensure compatibility between the features used on the mc68hc908as60a, mc68hc908az60a, and MC68HC908AZ60E and those which are available on the device which will ultimately be used in the application. for detailed information regarding the MC68HC908AZ60E refer to appendix b MC68HC908AZ60E . 1.2 features features of the mc68hc908as60a and mc68hc908az60a include: ? high-performance m68hc08 architecture ? fully upward-compatible object code wi th m6805, m146805, and m68hc05 families ? 8.4 mhz internal bus frequency ? 60 kbytes of flash electrically erasable read-only memory (flash) ? flash data security ? 1 kbyte of on-chip electrically erasable progr ammable read-only memory with security option (eeprom) ? 2 kbyte of on-chip ram ? clock generator module (cgm) ? serial peripheral interface module (spi) ? serial communications interface module (sci) ? 8-bit, 15-channel analog-to-digital converter (adc-15) ? 16-bit, 6-channel timer interface module (tima-6) ? programmable interrupt timer (pit) ? system protection features ? computer operating properly (cop) with optional reset ? low-voltage detection with optional reset ? illegal opcode detection with optional reset ? illegal address detection with optional reset ? low-power design (fully static with stop and wait modes) general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 22 freescale semiconductor ? master reset pin and power-on reset ? 16-bit, 2-channel timer inte rface module (timb) (az only) ? 5-bit keyboard interrupt module (64-pin qfp only) ? mscan controller implements can 2.0b protocol as defined in bosch specification september 1991 (az only) ? sae j1850 byte data link cont roller digital module (as only) features of the cpu08 include: ? enhanced hc05 programming model ? extensive loop control functions ? 16 addressing modes (eight more than the hc05) ? 16-bit index register and stack pointer ? memory-to-memory data transfers ? fast 8 8 multiply instruction ? fast 16/8 divide instruction ? binary-coded decimal (bcd) instructions ? optimization for controller applications ? c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908az60a. figure 1-2 shows the structure of the mc68hc908as60a. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 23 mcu block diagram figure 1-1. mcu block diagram for the mc68hc908az60a (64-pin qfp) break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module timer a 6 channel interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 62 bytes user flash ? 60 kbytes user ram ? 2048bytes user eeprom ? 1024 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptg ddrg osc1 osc2 cgmxfc rst irq v dd v dda v ssa pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tach1 pte2/tach0 pte1/rxd pte0/txd ptf5/tbch1?ptf4/tbch0 ptf3/tach5-ptf0/tach2 ptf ddrf ptg2/kbd2?ptg0/kbd0 power pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc5?ptc3 ptc2/mclk ptc1?ptc0 v refh mscan module timer b interface module canrx cantx pth ddrh pth1/kbd4?pth0/kbd3 keyboard interrupt module v ss user flash vector space ? 52 bytes ptf6 v ddaref av ss /v refl ptd3/atd11-ptd0/atd8 ptd6/atd14/taclk ptd5/atd13 ptd4/atd12/tbclk ptd7 programmable interrupt timer module mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 24 freescale semiconductor general description figure 1-2. mcu block diagram for the mc68hc908as60a (64-pin qfp and 52-pin plcc) break module clock generator module system integration module analog-to-digital module serial communications interface module serial peripheral interface module timer a 6 channel interface module low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 62 bytes user flash ? 60 kbytes user ram ? 2048bytes user eeprom ? 1024 bytes monitor rom ? 256 bytes irq module ddrd ptd ddre pte ptg* ddrg osc1 osc2 cgmxfc rst irq v dd v dda v ssa pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tach1 pte2/tach0 pte1/rxd pte0/txd ptf5/tbch1?ptf4/tbch0* ptf3/tach5-ptf0/tach2 ptf ddrf ptg2/kbd2?ptg0/kbd0* power pta ddra ddrb ptb ddrc ptc pta7?pta0 ptb7/atd7?ptb0/atd0 ptc5* ptc2/mclk ptc1?ptc0 v refh pth* ddrh pth1/kbd4?pth0/kbd3* keyboard interrupt module* v ss user flash vector space ? 52 bytes ptf6* v ddaref av ss /v refl ptd3/atd11-ptd0/atd8 ptd6/atd14/taclk ptd5/atd13 ptd4/atd12/tbclk ptd7* bdtxd bdrxd byte data link controller programmable interrupt timer module * = feature only available on the 64-pin qfp mc68hc908as60a ptc4 ptc3 pin assignments mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 25 1.4 pin assignments figure 1-3 shows the mc68hc908az60a pin assignments. figure 1-3. mc68hc908az60a (64-pin qfp) ptf4/tbch0 cgmxfc ptb7/atd7 ptf3/tach5 ptf2/tach4 ptf1/tach3 ptf0/tach2 rst irq ptc4 canrx cantx ptf5/tbch1 pte0/txd pte1/rxd pte2/tach0 pte3/tach1 pth0/kbd3 ptd3/atd11 ptd2/atd10 av ss /v refl v ddaref ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda v refh ptd7 ptd6/atd14/taclk ptd5/atd13 ptd4/atd12/tbclk pth1/kbd4 ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd ptg0/kbd0 ptg1/kbd1 ptg2/kbd2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ptf6 48 49 general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 26 freescale semiconductor figure 1-4 shows the mc68hc908as60a 64-pin qfp pin assignments. figure 1-4. mc68hc908as60a (64-pin qfp) ptf4 cgmxfc ptb7/atd7 ptf3/tach5 ptf2/tach4 ptf1/tach3 ptf0/tach2 rst irq ptc4 bdrxd bdtxd ptf5 pte0/txd pte1/rxd pte2/tach0 pte3/tach1 pth0/kbd3 ptd3/atd11 ptd2/atd10 av ss /v refl v ddaref ptd1/atd9 ptd0/atd8 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda v refh ptd7 ptd6/atd14/taclk ptd5/atd13 ptd4/atd12 pth1/kbd4 ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd ptg0/kbd0 ptg1/kbd1 ptg2/kbd2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ptf6 48 49 pin assignments mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 27 figure 1-5 shows mc68hc908as60a 52-pin plcc pin assignments. figure 1-5. mc68hc908as60a (52-pin plcc) 46 34 bdrxd cgmxfc ptb4/atd4 ptf3/tach5 ptf2/tach4 ptf1/tach3 ptf0/tach2 rst irq ptc4 bdtxd pte0/txd pte1/rxd pte2/tach0 pte3/tach1 ptd3/atd11 ptd2/atd10 ptd1/atd9 ptd0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa /v refl v dda /v ddaref v refh ptd6/atd14/taclk ptd5/atd13 ptd4/atd12 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte5/miso pte4/ss pte6/mosi pte7/spsck v ss v dd pta0 pta1 pta2 pta3 pta4 pta5 pta6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 45 44 43 42 41 40 39 38 37 36 35 7 6 5 4 3 2 1 52 51 50 49 48 47 general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 28 freescale semiconductor note the following pin descriptions are just a quick reference. for a more detailed representation, see chapter 22 input/output ports . 1.4.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to prov ide power supply bypassing at the mcu as shown in figure 1-6 . place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency response ceramic capacitor for c1. c2 is an optional bu lk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 1-6. power supply bypassing v ss is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). see chapter 19 serial peripheral interface (spi) . note v ss must be grounded for proper mcu operation. 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. see chapter 10 clock generator module (cgm) . 1.4.3 external reset pin (rst ) a 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. see chapter 9 system integration module (sim) for more information. 1.4.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. see chapter 17 external interrupt module (irq) . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typica l applications. pin assignments mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 29 1.4.5 analog power supply pin (v dda ) v dda is the power supply pin for the analog porti on of the clock generator module (cgm). see chapter 10 clock generator module (cgm) . 1.4.6 analog ground pin (v ssa ) v ssa is the ground connection for the analog portion of the clock generator module (cgm). see chapter 10 clock generator module (cgm) . 1.4.7 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cloc k generator module (cgm). see chapter 10 clock generator module (cgm) . 1.4.8 adc analog power supply pin (v ddaref ) v ddaref is the power supply pin for the analog portion of the analog-to-digital converter (adc). see chapter 26 analog-to-digital converter (adc) . 1.4.9 adc analog ground pin (av ss /v refl ) the av ss /v refl pin provides both the analog ground connecti on and the reference low voltage for the analog-to-digital converter (adc). see chapter 26 analog-to-digital converter (adc) . 1.4.10 adc refer ence high voltage pin (v refh ) v refh provides the reference high voltage for the analog-to-digital converter (adc). see chapter 26 analog-to-digital converter (adc) . 1.4.11 port a input/outp ut (i/o) pins (pta7?pta0) pta7?pta0 are general-purpose bidirectional i/o port pins. see chapter 22 input/output ports . 1.4.12 port b i/o pi ns (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (adc). see chapter 26 analog-to-digital converter (adc) and chapter 22 input/output ports . 1.4.13 port c i /o pins (ptc5?ptc0) ptc5 ? ptc3 and ptc1 ? ptc0 are general-purpose bidirectional i/o port pins. ptc2/mclk is a special function port that shares its pin wi th the system clock which has a fr equency equivalent to the system clock. see chapter 22 input/output ports . 1.4.14 port d i/o pins (ptd7?ptd0/atd8) port d is an 8-bit special-function port that shares seven of its pins with the analog-to-digital converter module (adc-15), one of its pins with the timer interf ace module a (tima), and one more of its pins with the timer interface module b (timb). see chapter 25 timer interface module a (tima) , chapter 20 timer interface module b (timb) , chapter 26 analog-to-digital converter (adc) and chapter 22 input/output ports . general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 30 freescale semiconductor 1.4.15 port e i/o pi ns (pte7/spsck ?pte0/txd) port e is an 8-bit special function port that shares two of its pins with the timer interface module a (tima), four of its pins with the serial peripheral interfac e module (spi), and two of its pins with the serial communication interface module (sci). see chapter 18 serial communications interface (sci) , chapter 19 serial peripheral interface (spi) , chapter 25 timer interface module a (tima) , and chapter 22 input/output ports . 1.4.16 port f i/ o pins (ptf6?ptf0/tach2) port f is a 7-bit special function port that shares its pins with the timer interface module b (timb). six of its pins are shared with the time r interface module a (tima-6). see chapter 25 timer interface module a (tima) , chapter 20 timer interface module b (timb) , and chapter 22 input/output ports . 1.4.17 port g i/o pins (ptg2/kbd2?ptg0/kbd0) port g is a 3-bit special function port that shares all of its pins with the keyboard module (kbd). see chapter 24 keyboard module (kbi) and chapter 22 input/output ports . 1.4.18 port h i/o pi ns (pth1/kbd4?pth0/kbd3) port h is a 2-bit special-function port that shares all of its pins with the keyboard module (kbd). see chapter 24 keyboard module (kbi) and chapter 22 input/output ports . 1.4.19 can tr ansmit pin (cantx) this pin is the digital output from the can module (cantx). see chapter 23 mscan controller (mscan08) . 1.4.20 can r eceive pin (canrx) this pin is the digital input to the can module (canrx). see chapter 23 mscan controller (mscan08) . 1.4.21 bdlc tran smit pin (bdtxd) this pin is the digital output from the bdlc module (bdtxd). see chapter 27 byte data link controller (bdlc) . 1.4.22 bdlc r eceive pin (bdrxd) this pin is the digital input to the can module (bdrxd). see chapter 27 byte data link controller (bdlc) . pin assignments mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 31 table 1-1. external pins summary pin name function driver type hysteresis (1) reset state pta7?pta0 general-purpose i/o dual state no input hi-z ptb7/atd7?ptb0/atd0 general-purpose i/o adc channel dual state no input hi-z ptc5?ptc0 general-purpose i/o dual state no input hi-z ptd7 general purpose i/o dual state no input hi-z ptd6/atd14/taclk adc channel general-purpose i/o adc channel/ timer external input clock dual state no input hi-z ptd5/atd13 adc channel general-purpose i/o adc channel dual state no input hi-z ptd4/atd12/tbclk adc channel general-purpose i/o adc channel/ timer external input clock dual state no input hi-z ptd3/atd11?ptd0/atd8 adc channels general-purpose i/o adc channel dual state no input hi-z pte7/spsck general-purpose i/o spi clock dual state open drain yes input hi-z pte6/mosi general-purpose i/o spi data path dual state open drain yes input hi-z pte5/miso general-purpose i/o spi data path dual state open drain yes input hi-z pte4/ss general-purpose i/o spi slave select dual state yes input hi-z pte3/tach1 general-purpose i/o timer a channel 1 dual state yes input hi-z pte2/tach0 general-purpose i/o timer a channel 0 dual state yes input hi-z pte1/rxd general-purpose i/o sci receive data dual state yes input hi-z pte0/txd general-purpose i/o sci transmit data dual state no input hi-z ptf6 general-purpose i/o dual state no input hi-z ptf5/tbch1?ptf4/tbch0 general-purpose i/o/ timer b channel dual state yes input hi-z ptf3/tach5 general-purpose i/o timer a channel 5 dual state yes input hi-z ptf2/tach4 general-purpose i/o timer a channel 4 dual state yes input hi-z ptf1/tach3 general-purpose i/o timer a channel 3 dual state yes input hi-z ? continued on next page general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 32 freescale semiconductor ptf0/tach2 general-purpose i/o timer a channel 2 dual state yes input hi-z ptg2/kbd2?ptg0/kbd0 general-purpose i/o/ keyboard wakeup pin dual state yes input hi-z pth1/kbd4 ?pth0/kbd3 general-purpose i/o/ keyboard wakeup pin dual state yes input hi-z v dd chip power supply n/a n/a n/a v ss chip ground n/a n/a n/a v dda cgm analog power supply v ssa cgm analog ground v ddaref adc power supply n/a n/a n/a a vss /v refl adc ground/ adc reference low voltage n/a n/a n/a v refh a/d reference high voltage n/a n/a n/a osc1 external clock in n/a no input hi-z osc2 external clock out n/a n/a output cgmxfc pll loop filter cap n/a n/a n/a irq external interrupt request n/a n/a input hi-z rst reset n/a n/a output low canrx can serial input n/a yes input hi-z cantx can serial output output no output bdrxd bdlc serial input n/a yes input hi-z bdtxd bdlc serial output output no output 1. hysteresis is not 100% tested but is typically a minimum of 300 mv. table 1-1. external pins summary (continued) pin name function driver type hysteresis (1) reset state pin assignments mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 33 table 1-2. clock signal naming conventions clock signal name description cgmxclk buffered version of osc1 from clock generation module (cgm) cgmout pll-based or osc1-based clock output from clock generator module (cgm) bus clock cgmout divided by two spsck spi serial clock taclk external clock input for tima tbclk external clock input for timb table 1-3. clock source summary module clock source adc cgmxclk or bus clock can cgmxclk or cgmout cop cgmxclk cpu bus clock flash bus clock eeprom cgmxclk or bus clock ram bus clock spi bus clock/spsck sci cgmxclk tima bus clock or ptd6/atd14/taclk timb bus clock or ptd4/tbclk pit bus clock sim cgmout and cgmxclk irq bus clock brk bus clock lvi bus clock and cgmxclk cgm osc1 and osc2 general description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 34 freescale semiconductor 1.5 ordering information this subsection contains inst ructions for ordering the mc68hc908az60a / mc68hc908as60a. table 1-4. mc order numbers mc order number operating temperature range mc68hc908as60acfu (64-pin qfp) ?40 c to + 85 c mc68hc908as60avfu (64-pin qfp) ?40 c to + 105 c mc68hc908as60amfu (64-pin qfp) ?40 c to + 125 c mc68hc908as60acfn (52-pin plcc) ?40 c to + 85 c mc68hc908as60avfn (52-pin plcc) ?40 c to + 105 c mc68hc908as60amfn (52-pin plcc) ?40 c to + 125 c mc68hc908az60acfu (64-pin qfp) ?40 c to + 85 c mc68hc908az60avfu (64-pin qfp) ?40 c to + 105 c mc68hc908az60amfu (64-pin qfp) ?40 c to + 125 c mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 35 chapter 2 memory map 2.1 introduction the cpu08 can address 64k bytes of memory space. the memory map, shown in figure 2-1 , includes: ? 60k bytes of flash eeprom ? 2048 bytes of ram ? 1024 bytes of eeprom with protect option ? 52 bytes of user-defined vectors ? 256 bytes of monitor rom the following definitions apply to the memory map representation of reserved and unimplemented locations. ? reserved ? accessing a reserved location can have unpredictable effects on mcu operation. ? unused ? these locations are reserved in the memory map for future use , accessing an unused location can have unpredictable effects on mcu operation. ? unimplemented ? accessing an unimplemented locati on can cause an illegal address reset (within the constraints as outlined in the chapter 9 system integration module (sim) ). memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 36 freescale semiconductor mc68hc908az60a mc68hc908as60a $0000 i/o registers 64 bytes $0000 $003f $003f $0040 i/o registers 16 bytes unimplemented 11 bytes $0040 $004a i/o registers 5 bytes $004b $004f $004f $0050 ram-1 1024 bytes $0050 $044f $044f $0450 flash-2 176 bytes flash-2 432 bytes $0450 $04ff $0500 can control and message buffers 128 bytes $057f $0580 flash-2 128 bytes $05ff $05ff $0600 eeprom-2 512 bytes $0600 $07ff $07ff $0800 eeprom-1 512 bytes $0800 $09ff $09ff $0a00 ram-2 1024 bytes $0a00 $0dff $0dff $0e00 flash-2 29,184 bytes $0e00 $7fff $7fff $8000 flash-1 32,256bytes $8000 $fdff $fdff $fe00 sim break status register (sbsr) $fe00 $fe01 sim reset status register (srsr) $fe01 $fe02 reserved $fe02 figure 2-1. memory map (sheet 1 of 3) introduction mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 37 $fe03 sim break flag contro l register (sbfcr) $fe03 $fe04 reserved $fe04 $fe05 reserved $fe05 $fe06 reserved $fe06 $fe07 reserved $fe07 $fe08 flash-2 control register (fl2cr) $fe08 $fe09 configuration write-once regiser (config-2) $fe09 $fe0a reserved $fe0a $fe0b reserved $fe0b $fe0c break address regist er high (brkh) $fe0c $fe0d break address register low (brkl) $fe0d $fe0e break status and control register (bscr) $fe0e $fe0f lvi status register (lvisr) $fe0f $fe10 eeprom-1eedivh nonvolatile register(ee1divhnvr) $fe10 $fe11 eeprom-1eedivl nonvolatile register(ee1divlnvr) $fe11 $fe12 reserved $fe12 $fe13 reserved $fe13 $fe14 reserved $fe14 $fe15 reserved $fe15 $fe16 reserved $fe16 $fe17 reserved $fe17 $fe18 reserved $fe18 $fe19 reserved $fe19 $fe1a eeprom-1 ee divider hi gh register(ee1divh) $fe1a $fe1b eeprom-1 ee divider low register(ee1divl) $fe1b $fe1c eeprom-1 eeprom nonvolatile register (ee1nvr) $fe1c $fe1d eeprom-1 eeprom contro l register (ee1cr) $fe1d $fe1e reserved $fe1e $fe1f eeprom-1 eeprom array config uration register (ee1acr) $fe1f $fe20 monitor rom 256bytes $fe20 $ff1f $ff1f $ff20 $ff6f unimplemented 80 bytes $ff20 $ff6f $ff70 eeprom-2 eedivh nonvolatile register (ee2divhnvr) $ff70 $ff71 eeprom-2 eedivl nonvolatile register (ee2divlnvr) $ff71 $ff72 reserved $ff72 $ff73 reserved $ff73 $ff74 reserved $ff74 mc68hc908az60a mc68hc908as60a figure 2-1. memory map (sheet 2 of 3) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 38 freescale semiconductor $ff75 reserved $ff75 $ff76 reserved $ff76 $ff77 reserved $ff77 $ff78 reserved $ff78 $ff79 reserved $ff79 $ff7a eeprom-2 ee divider high register (ee2divh) $ff7a $ff7b eeprom-2 ee divider lo w register (ee2divl) $ff7b $ff7c eeprom-2 eeprom nonvolatile register (ee2nvr) $ff7c $ff7d eeprom-2 eeprom contro l register (ee2cr) $ff7d $ff7e reserved $ff7e $ff7f eeprom-2 eeprom array config uration register (ee2acr) $ff7f $ff80 flash-1 block protec t register (f l1bpr) $ff80 $ff81 flash-2 block protec t register (f l2bpr) $ff81 $ff82 reserved 6 bytes $ff82 $ff87 $ff87 $ff88 flash-1 control register (fl1cr) $ff88 $ff89 reserved $ff89 $ff8a reserved $ff8a $ff8b reserved 65 bytes $ff8b $ffcb $ffcb $ffcc $ffcc vectors 52 bytes see table 2-1 $ffff $ffff 1. registers appearing in italics are for freescale test pur pose only and only appear in the memory map for reference. 2. while some differences between mc68hc908as60a and mc68hc908az60a are highlighted, some registers re- main available on both parts. refer to individual modules for details whether these registers are active or inactive. mc68hc908az60a mc68hc908as60a figure 2-1. memory map (sheet 3 of 3) i/o section mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 39 2.2 i/o section addresses $0000?$004f, shown in figure 2-2 , contain the i/o data, status, and control registers. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 write: $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: $0009 port f data register (ptf) read: 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r $000a port g data register (ptg) read:00000 ptg2 ptg1 ptg0 write:rrrrr $000b port h data register (pth) read:000000 pth1 pth0 write:rrrrrr $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: $000d data direction register f (ddrf) read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r $000e data direction register g (ddrg) read:00000 ddrg2 ddrg1 ddrg0 write:rrrrr $000f data direction register h (ddrh) read:000000 ddrh1 ddrh0 write:rrrrrr = unimplemented r = reserved figure 2-2. i/o data, status and control registers (sheet 1 of 5) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 40 freescale semiconductor $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: $0012 spi data register (spdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: $0017 sci status register 2 (scs2) read: 0 0 0 0 0 0 bkf rpf write: $0018 sci data register (scdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: $001a irq status and control register (iscr) read: 0 0 0 0 irqf 0 imask mode write:rrrr ack $001b keyboard status and control register (kbscr) read: 0 0 0 0 keyf 0 imaskk modek write: ackk $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: $001f configuration write-once register (config-1) read: lvistop r lvirst lvipwr ssrec copl stop copd write: $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o data, status and control registers (sheet 2 of 5) i/o section mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 41 $0021 keyboard interrupt enable register (kbier) read:000 kbie4 kbie3 kbie2 kbie1 kbie0 write: $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $0023 timer a counter register low (tacntl) read:bit 7654321bit 0 write: $0024 timer a modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: $0025 timer a modulo register low (tamodl) read: bit 7 6 5 4 3 2 1 bit 0 write: $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0028 timer a channel 0 register low (tach0l) read: bit 7 6 5 4 3 2 1 bit 0 write: $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: $002b timer a channel 1 register low (tach1l) read: bit 7 6 5 4 3 2 1 bit 0 write: $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: $002e timer a channel 2 register low (tach2l) read: bit 7 6 5 4 3 2 1 bit 0 write: $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0031 timer a channel 3 register low (tach3l) read: bit 7 6 5 4 3 2 1 bit 0 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o data, status and control registers (sheet 3 of 5) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 42 freescale semiconductor $0032 timer a channel 4 status and control register (tasc4) read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 $0033 timer a channel 4 register high (tach4h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0034 timer a channel 4 register low (tach4l) read: bit 7 6 5 4 3 2 1 bit 0 write: $0035 timer a channel 5 status and control register (tasc5) read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r $0036 timer a channel 5 register high (tach5h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0037 timer a channel 5 register low (tach5l) read: bit 7 6 5 4 3 2 1 bit 0 write: $0038 analog-to-digital status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r $0039 analog-to-digital data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: $003a analog-to-digital input clock register (adiclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: $003b bdlc analog and roundtrip delay register (bard) read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r $003c bdlc control register 1 (bcr1) read: imsg clks r1 r0 00 ie wcm write: r r $003d bdlc control register 2 (bcr2) read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: $003e bdlc state vector register (bsvr) read:0 0 i3i2i1i0 0 0 write:rrrrrrrr $003f bdlc data register (bdr) read: bd7bd6bd5bd4bd3bd2bd1bd0 write: $0040 timer b status and control register (tbscr) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $0042 timer b counter register low (tbcntl) read:bit 7654321bit 0 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o data, status and control registers (sheet 4 of 5) i/o section mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 43 all registers are shown for both mc68hc908as60a and mc68hc908az60a. refer to individual module chapters to determine if the module is available and the register active or not. $0043 timer b modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: $0044 timer b modulo register low (tbmodl) read: bit 7 6 5 4 3 2 1 bit 0 write: $0045 timer b ch0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 $0046 timer b ch0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0047 timer b ch0 register low (tbch0l) read: bit 7 6 5 4 3 2 1 bit 0 write: $0048 timer b ch1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r $0049 timer b ch1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: $004a timer b ch1 register low (tbch1l) read: bit 7 6 5 4 3 2 1 bit 0 write: $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $004d pit counter register low (pcntl) read:bit 7654321bit 0 write: $004e pit modul o register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: $004f pit modulo register low (pmodl) read: bit 7 6 5 4 3 2 1 bit 0 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. i/o data, status and control registers (sheet 5 of 5) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 44 freescale semiconductor 2.3 additional status and control registers selected addresses in the range $fe00 to $ffcb c ontain additional status and control registers as shown in figure 2-3 . a noted exception is the cop control register (copctl) at address $ffff. addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr bw r write: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: $fe08 flash-2 control register (fl2cr) read:0000 hven verf erase pgm write: $fe09 configuration write-once register (config-2) read: eedivclk r r mscand at6 0a rrazxx write: r $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: $fe0d break address register low (brkl) read: bit 7654321bit 0 write: $fe0e break status and control register (brkscr) read: brke brka 000000 write: $fe0f lvi status register (lvisr) read:lviout0000000 write: $fe10 ee1div hi nonvolatile register (ee1divhnvr) read: write: eedivs- ecd rrrreediv10eediv9eediv8 $fe11 ee1div lo nonvolatile register (ee1divlnvr) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $fe1a ee1div divider high register (ee1divh) read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: $fe1b ee1div divider low register (ee1divl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $fe1c eeprom-1 nonvolatile register (ee1nvr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $fe1d eeprom-1 control register (ee1cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: = unimplemented r = reserved figure 2-3. additional status and control registers (sheet 1 of 2) additional status and control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 45 $fe1f eeprom-1 array configura- tion register (ee1acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $ff70 ee2div hi nonvolatile register (ee2divhnvr) read: eedivs- ecd rrrreediv10eediv9eediv8 write: $ff71 ee2div lo nonvolatile register (ee2divlnvr) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $ff7a ee2div divider high register (ee2divh) read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: $ff7b ee2div divider low register (ee2divl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $fe7c eeprom-2 nonvolatile register (ee2nvr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $fe7d eeprom-2 control register (ee2cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: $fe7f eeprom-2 array configuration register (ee2acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $ff80 flash-1 block protect register (fl1bpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: $ff81 flash-2 block protect register (fl2bpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: $ff88 flash-1 control register (fl1cr) read:0000 hven verf erase pgm write: $ffff cop control register (copctl) read: low byte of reset vector write: writing to $ffff clears cop counter addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-3. additional status and control registers (sheet 2 of 2) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 46 freescale semiconductor 2.4 vector addr esses and priority addresses in the range $ffcc to $ffff contain the user-specified vector locations. the vector addresses are shown in table 2-1 . please note that certain vector addresses differ between the mc68hc908as60a and the mc68hc908az60a as shown in the table. it is recommended that all vector addresses are defined. table 2-1. vector addresses vector address mc68hc908az60a mc68hc908as60a lowest priority $ffcc tima channel 5 vector (high) reserved $ffcd tima channel 5 vector (low) reserved $ffce tima channel 4 vector (high) reserved $ffcf tima channel 4 vector (low) reserved $ffd0 adc vector (high) reserved $ffd1 adc vector (low) reserved $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) reserved $ffd5 sci transmit vector (low) reserved $ffd6 sci receive vector (high) reserved $ffd7 sci receive vector (low) reserved $ffd8 sci error vector (high) reserved $ffd9 sci error vector (low) reserved $ffda can transmit vector (high) pit vector (high) $ffdb can transmit vector (low) pit vector (low) $ffdc can receive vector (high) bdlc vector (high) $ffdd can receive vector (low) bdlc vector (low) $ffde can error vector (high) adc vector (high) $ffdf can error vector (low) adc vector (low) $ffe0 can wakeup vector (high) sci transmit vector (high) $ffe1 can wakeup vector (low) sci transmit vector (low) $ffe2 spi transmit vector (high) sci receive vector (high) $ffe3 spi transmit vector (low) sci receive vector (low) $ffe4 spi receive vector (high) sci error vector (high) $ffe5 spi receive vector (l ow) sci error vector (low) $ffe6 timb overflow vector (hig h) spi transmit vector (high) $ffe7 timb overflow vector (low) spi transmit vector (low) $ffe8 timb ch1 vector (high) spi receive vector (high) $ffe9 timb ch1 vector (low) spi receive vector (low) $ffea timb ch0 vector (high) tima overflow vector (high) $ffeb timb ch0 vector (low) tima overflow vector (low) $ffec tima overflow vector (high) tima channel 5 vector (high) vector addresses and priority mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 47 $ffed tima overflow vector (low) tima channel 5 vector (low) $ffee tima ch3 vector (high) tima channel 4 vector (high) $ffef tima ch3 vector (low) tima channel 4 vector (low) $fff0 tima ch2 vector (high) tima channel 3 vector (high) $fff1 tima ch2 vector (low) tima channel 3 vector (low) $fff2 tima ch1 vector (high) tima channel 2 vector (high) $fff3 tima ch1 vector (low) tima channel 2 vector (low) $fff4 tima ch0 vector (high) tima channel 1 vector (high) $fff5 tima ch0 vector (low) tima channel 1 vector (low) $fff6 pit vector (high) tima channel 0 vector (high) $fff7 pit vector (low) tim a channel 0 vector (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) highest priority $ffff reset vector (low) table 2-1. vector addresses (continued) vector address mc68hc908az60a mc68hc908as60a memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 48 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 49 chapter 3 random-access memory (ram) 3.1 introduction this chapter describes the 2048 by tes of random-access memory (ram). 3.2 functional description addresses $0050 through $044f and $0a00 through $0dff are ram locations. the location of the stack ram is programmable with the reset stack pointer in struction (rsp). the 16-bit stack pointer allows the stack ram to be anywhere in the 64k-byte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for input/output (i/o ) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access all page zero ram locations efficiently. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m68hc05, m6805, and m146805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subroutines. the cpu could overwrite data in the ram during a subroutine or dur ing the interrupt stacking operation. random-access memory (ram) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 50 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 51 chapter 4 flash-1 memory 4.1 introduction this chapter describes the operation of the embedded flash-1 memory. this memory can be read, programmed and erased from a single external s upply. the program and erase operations are enabled through the use of an internal charge pump. 4.2 functional description the flash-1 memory is an array of 32,256 bytes with two bytes of block protection (one byte for protecting areas within flash-1 array and one byte for protecting areas within flash-2 array) and an additional 40 bytes of user vectors on the mc68hc 908as60a and 52 bytes of user vectors on the mc68hc908az60a. an erased bit reads as a l ogic 1 and a programmed bit reads as a logic 0. memory in the flash-1 array is organized into rows within pages. there are two rows of memory per page with 64 bytes per row. the minimum erase bl ock size is a single page, 128 bytes. programming is performed on a per-row basis, 64 bytes at a time. pr ogram and erase operations are facilitated through control bits in the flash-1 control register (fl1cr) . details for these operations appear later in this chapter. the flash-1 memory map consists of: ? $8000?$fdff: user memory (32,256 bytes) ? $ff80: flash-1 block protect register (fl1bpr) ? $ff81: flash-2 block protect register (fl2bpr) ? $ff88: flash-1 control register (fl1cr) ? $ffcc?$ffff: these locations are reserved for user-defined interrupt and reset vectors. (please see 2.4 vector addresses and priority for details) programming tools are available from freescale. cont act your local freescale representative for more information. note a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. flash-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 52 freescale semiconductor 4.3 flash-1 control and block protect registers the flash-1 array has two registers that control its operation, the flash-1 control register (fl1cr) and the flash-1 block protect register (fl1bpr). 4.3.1 flash-1 control register the flash-1 control register (fl1cr) controls flash-1 program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the fl ash-1 array for mass or page erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected address: $ff88 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-1. flash-1 control register (fl1cr) flash-1 control and block protect registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 53 4.3.2 flash-1 bl ock protect register the flash-1 block protect register (fl1bpr) is im plemented as a byte within the flash-1 memory and therefore can only be written during a flash pr ogramming sequence. the value in this register determines the starting location of the protected range within the flash-1 memory. fl1bpr[7:0] ? block protect register bit 7 to bit 0 these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is logic 1 and bits [6:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash-1 memory for block protection. flash-1 is protected from this start address to the end of flash-1 memory at $ffff. with this mechanism, the protect start addres s can be $xx00 and $xx80 (128 byte page boundaries) within the flash-1 array. figure 4-3. flash-1 block protect start address flash-1 protected ranges address: $ff80 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: figure 4-2. flash-1 block protect register (fl1bpr) fl1bpr[7:0] protected range $ff no protection $fe $ff00 ? $ffff $fd $fe80 ? $ffff $0b $8580 ? $ffff $0a $8500 ? $ffff $09 $8480 ? $ffff $08 $8400 ? $ffff $04 $8200 ? $ffff $03 $8180 ? $ffff $02 $8100 ? $ffff $01 $8080 ? $ffff $00 $8000 ? $ffff 1 flbpr value 16-bit memory address 0000000 start address of flash block protect flash-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 54 freescale semiconductor decreasing the value in fl1bpr by one increa ses the protected range by one page (128 bytes). however, programming the block protect register with $fe protects a range twice that size, 256 bytes, in the corresponding array. $fe means that locations $ff00?$ffff are protected in flash-1. the flash memory does not exist at some location s. the block protection range configuration is unaffected if flash memory does not exist in that range. refer to the memory map and make sure that the desired locations are protected. 4.4 flash-1 block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is done by using the flash-1 block protection register (fl1bpr). fl1bpr determines the range of the flash-1 memory which is to be protected. the range of the protected area starts from a locati on defined by fl1bpr and ends at the bottom of the flash-1 memory ($ffff). when the memory is protected, the hven bit can not be set in either erase or program operations. note in performing a program or erase operation, the flash-1 block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flash-1 block protect register is programm ed with all 0?s, the entir e memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within fl1bpr are programmed (logic 0) , they lock a block of memory address ranges as shown in 4.3.2 flash-1 block protect register . if fl1bpr is programmed with any value other than $ff, the protected block of flash memory can not be erased or programmed. note the vector locations and the flash block protect registers are located in the same page. fl1bpr and fl2bpr are not protected with special hardware or software; therefore, if this page is not protected by fl1bpr and the vector locations are erased by either a page or a mass erase operation, both fl1bpr and fl2bpr will also get erased. flash-1 mass erase operation mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 55 4.5 flash-1 mass erase operation use this step-by-step procedure to erase the entire flash-1 memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash-1 control register (fl1cr). 2. read the flash-1 block protect register (fl1bpr). 3. write to any flash-1 address within the flash-1 array with any data. note if the address written to in step 3 is within address space protected by the flash-1 block protect register (fl1bpr), no erase will occur. 4. wait for a time, t nvs . 5. set the hven bit. 6. wait for a time, t merase . 7. clear the erase bit. 8. wait for a time, t nvhl . 9. clear the hven bit. 10. wait for a time, t rcv , after which the memory can be accessed in normal read mode. note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. flash-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 56 freescale semiconductor 4.6 flash-1 page erase operation use this step-by-step procedure to erase a page (128 bytes) of flash-1 memory to read as logic 1: 1. set the erase bit and clear the mass bit in the flash-1 control register (fl1cr). 2. read the flash-1 block protect register (fl1bpr). 3. write any data to any flash-1 address within the address range of the page (128 byte block) to be erased. 4. wait for time, t nvs . 5. set the hven bit. 6. wait for time, t erase . 7. clear the erase bit. 8. wait for time, t nvh . 9. clear the hven bit. 10. wait for a time, t rcv , after which the memory can be accessed in normal read mode. note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. 4.7 flash-1 program operation programming of the flash memory is done on a row basi s. a row consists of 64 consecutive bytes with address ranges as follows: ? $xx00 to $xx3f ? $xx40 to $xx7f ? $xx80 to $xxbf ? $xxc0 to $xxff during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. use this step-by-step procedure to program a row of flash-1 memory. note in order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit in the flash-1 control register (fl1cr). this configures the memory for program operation and enables the latching of address and data programming. 2. read the flash-1 block protect register (fl1bpr). flash-1 program operation mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 57 3. write to any flash-1 address within the row address range desired with any data. 4. wait for time, t nvs . 5. set the hven bit. 6. wait for time, t pgs . 7. write data byte to the flash-1 address to be programmed. 8. wait for time, t prog . 9. repeat step 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit. 11. wait for time, t nvh . 12. clear the hven bit. 13. wait for a time, t rcv , after which the memory can be accessed in normal read mode. the flash programming algorithm flowchart is shown in figure 4-4 . note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. d. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv max. please also see 28.1.14 flash memory characteristics . e. the time between each flash address change (step 7 to step 7), or the time between the last flash address programmed to clearing the pgm bit (step 7 to step 10) must not exceed the maximum programming time, t prog max. f. be cautious when programming the flash-1 array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. this applies particularly to: $ffd2-$ffd3 and $ffda-$ffff: vector area on mc68hc908as60a (40 bytes) $ffcc-$ffff: vector area on mc68hc908az60a (52 bytes) flash-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 58 freescale semiconductor figure 4-4. flash programming algorithm flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash addres s change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash addr ess programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed ar e initially erased. low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 59 4.8 low-power modes the wait and stop instructions will place the mcu in low power consumption standby modes. 4.8.1 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash. wait mode will suspend any flash progra m/erase operations and leave the memory in a standby mode. 4.8.2 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash. stop mode will suspend any flash program/erase operations and leave the memory in a standby mode. note standby mode is the power saving mode of the flash module, in which all internal control signals to the flash are inactive and the current consumption of the flash is minimum. flash-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 60 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 61 chapter 5 flash-2 memory 5.1 introduction this chapter describes the operation of the embedded flash-2 memory. this memory can be read, programmed and erased from a single external s upply. the program and erase operations are enabled through the use of an internal charge pump. 5.2 functional description the flash-2 memory is a non-continuos array co nsisting of a total of 29,616 bytes on the mc68hc908as60a and 29,488 bytes on the mc68hc 908az60a. an erased bit reads as a logic 1 and a programmed bit reads as a logic 0. memory in the flash-2 array is organized into rows within pages. there are two rows of memory per page with 64 bytes per row. the minimum erase bl ock size is a single page, 128 bytes. programming is performed on a per-row basis, 64 bytes at a time. pr ogram and erase operations are facilitated through control bits in the flash-2 control register (fl2cr) . details for these operations appear later in this chapter. the flash-2 memory map consists of: ? $0450?$05ff: user memory on mc68hc908as60a (432 bytes) ? $0450?$04ff: user memory on mc68hc908az60a (176 bytes) ? $0580?$05ff: user memory on mc68hc908az60a (128 bytes) ? $0e00?$7fff: user memory (29,616 bytes) ? $ff81: flash-2 block protect register (fl2bpr) note fl2bpr physically re sides within flash-1 memory addressing space ? $fe08: flash-2 control register (fl2cr) programming tools are available from freescale. cont act your local freescale representative for more information. note a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users. flash-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 62 freescale semiconductor 5.3 flash-2 control and block protect registers the flash-2 array has two registers that control its operation, the flash-2 control register (fl2cr) and the flash-2 block protect register (fl2bpr). 5.3.1 flash-2 control register the flash-2 control register (fl2cr) controls flash-2 program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the fl ash-2 array for mass or page erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be set at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 5.3.2 flash-2 bl ock protect register the flash-2 block protect register (fl2bpr) is im plemented as a byte within the flash-1 memory and therefore can only be written during a flash pr ogramming sequence. the value in this register determines the starting location of the protected range within the flash-2 memory. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 5-1. flash-2 control register (fl2cr) flash-2 control and block protect registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 63 note the flash-2 block protect register (fl2bpr) controls the block protection for the flash-2 array. however, fl2bpr is implemented within the flash-1 memory array and therefore, the flash-1 control register (fl1cr) must be used to program/erase fl2bpr. fl2bpr[7:0] ? block protect register bit 7 to bit 0 these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is logic 1 and bits [6:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash-2 memory for block protection. flash-2 is protected from this start address to the end of flash-2 memory at $7fff. with this mechanism, the protect start addres s can be $xx00 and $xx80 (128 byte page boundaries) within the flash-2 array. figure 5-3. flash-2 block protect start address flash-2 protected ranges: address: $ff81 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: figure 5-2. flash-2 block protect register (fl2bpr) fl2bpr[7:0] protected range $ff no protection $fe $7f00 ? $7fff $fd $7e80 ? $7fff $0b $0580 ? $7fff $0a $0500 ? $7fff $09 $0480 ? $7fff $08 $0450 ? $7fff $04 $0450 ? $7fff $03 $0450 ? $7fff $02 $0450 ? $7fff $01 $0450 ? $7fff $00 $0450 ? $7fff 1 flbpr value 16-bit memory address 0000000 start address of flash block protect flash-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 64 freescale semiconductor decreasing the value in fl2bpr by one increa ses the protected range by one page (128 bytes). however, programming the block protect register with $fe protects a range twice that size, 256 bytes, in the corresponding array. $fe means that locations $7f00?$7fff are protected in flash-2. the flash memory does not exist at some location s. the block protection range configuration is unaffected if flash memory does not exist in that range. refer to the memory map and make sure that the desired locations are protected. 5.4 flash-2 block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made fo r protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protec tion is done by using the flash-2 block protection register (fl2bpr). fl2bpr determines the range of the flash-2 memory which is to be protected. the range of the protected area starts from a locati on defined by fl2bpr and ends at the bottom of the flash-2 memory ($7fff). when the memory is protec ted, the hven bit can not be set in either erase or program operations. note in performing a program or erase operation, the flash-2 block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flash-2 block protect register is programm ed with all 0?s, the entir e memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within fl2bpr are programmed (logic 0) , they lock a block of memory address ranges as shown in 5.3.2 flash-2 block protect register . if fl2bpr is programmed with any value other than $ff, the protected block of flash memory can not be erased or programmed. note the vector locations and the flash block protect registers are located in the same page. fl1bpr and fl2bpr are not protected with special hardware or software; therefore, if this page is not protected by fl1bpr and the vector locations are erased by either a page or a mass erase operation, both fl1bpr and fl2bpr will also get erased. flash-2 mass erase operation mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 65 5.5 flash-2 mass erase operation use this step-by-step procedure to erase the entire flash-2 memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash-2 control register (fl2cr). 2. read the flash-2 block protect register (fl2bpr). 3. write to any flash-2 address within the flash-2 array with any data. note if the address written to in step 3 is within address space protected by the flash-2 block protect register (fl2bpr), no erase will occur. 4. wait for a time, t nvs . 5. set the hven bit. 6. wait for a time, t merase . 7. clear the erase bit. 8. wait for a time, t nvhl . 9. clear the hven bit. 10. wait for a time, t rcv , after which the memory can be accessed in normal read mode. note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. flash-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 66 freescale semiconductor 5.6 flash-2 page erase operation use this step-by-step procedure to erase a page (128 bytes) of flash-2 memory to read as logic 1: 1. set the erase bit and clear the mass bit in the flash-2 control register (fl2cr). 2. read the flash-2 block protect register (fl2bpr). 3. write any data to any flash-2 address within the address range of the page (128 byte block) to be erased. 4. wait for time, t nvs . 5. set the hven bit. 6. wait for time, t erase . 7. clear the erase bit. 8. wait for time, t nvh . 9. clear the hven bit. 10. wait for a time, t rcv , after which the memory can be accessed in normal read mode. note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. 5.7 flash-2 program operation programming of the flash memory is done on a row basi s. a row consists of 64 consecutive bytes with address ranges as follows: ? $xx00 to $xx3f ? $xx40 to $xx7f ? $xx80 to $xxbf ? $xxc0 to $xxff during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. ? use this step-by-step procedure to program a row of flash-2 memory. note in order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit in the flash-2 control register (fl2cr). this configures the memory for program operation and enables the latching of address and data programming. 2. read the flash-2 block protect register (fl2bpr). 3. write to any flash-2 address within the row address range desired with any data. flash-2 program operation mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 67 4. wait for time, t nvs . 5. set the hven bit. 6. wait for time, t pgs . 7. write data byte to the flash-2 address to be programmed. 8. wait for time, t prog . 9. repeat step 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit. 11. wait for time, t nvh . 12. clear the hven bit. 13. wait for a time, t rcv , after which the memory can be accessed in normal read mode. the flash programming algorithm flowchart is shown in figure 5-4 . note a. programming and erasing of flash locations can not be performed by code being executed from the same flash array. b. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. care must be taken however to ensure that these operati ons do not access any address within the flash array memory space such as the cop control register (copctl) at $ffff. c. it is highly recommended that interrupts be disabled during program/erase operations. d. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 64) t hv max. please also see 28.1.14 flash memory characteristics . e. the time between each flash address change (step 7 to step 7), or the time between the last flash address programmed to clearing the pgm bit (step 7 to step 10) must not exceed the maximum programming time, t prog max. f. be cautious when programming the flash-2 array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. this applies particularly to: $0450-$047f: first row of flash-2 (48 bytes) flash-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 68 freescale semiconductor figure 5-4. flash programming algorithm flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash addres s change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash addr ess programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed ar e initially erased. low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 69 5.8 low-power modes the wait and stop instructions will place the mcu in low power consumption standby modes. 5.8.1 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash. wait mode will suspend any flash progra m/erase operations and leave the memory in a standby mode. 5.8.2 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly; ho wever, no memory activity will ta ke place since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash. stop mode will suspend any flash program/erase operations and leave the memory in a standby mode. note standby mode is the power saving mode of the flash module, in which all internal control signals to the flash are inactive and the current consumption of the flash is minimum. flash-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 70 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 71 chapter 6 eeprom-1 memory 6.1 introduction this chapter describes the 512 bytes of electr ically erasable programmable read-only memory (eeprom) residing at address r ange $0800 to $09ff. there are 1 024 bytes of eeprom available on the mc68hc908as60a and mc68hc908az60a which are physically located in two 512 byte arrays. for information relating to the array coveri ng address range $0600 to $07ff please see chapter 7 eeprom-2 memory . 6.2 features features of the eeprom-1 include the following: ? 512 bytes nonvolatile memory ? byte, block, or bulk erasable ? nonvolatile eeprom configurati on and block protection options ? on-chip charge pump for programming/erasing ? security option ? auto bit driven programming/erasing time feature 6.3 eeprom-1 register summary the eeprom-1 register summary is shown in figure 6-1 . eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 72 freescale semiconductor addr.register name bit 7654321bit 0 $fe10 ee1div nonvolatile register high (ee1divhnvr) (1) read: eedivs- ecd rrrreediv10eediv9eediv8 write: reset: unaffected by reset; $ff when blank $fe11 ee1div nonvolatile register low (ee1divlnvr) (1) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank $fe1a ee1 divider register high (ee1divh) read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: reset: contents of ee1divhnvr ($fe10), bits [6:3] = 0 $fe1b ee1 divider register low (ee1divl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of ee1divlnvr ($fe11) $fe1c eeprom-1 nonvolatile register (ee1nvr) (1) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $f0 $fe1d eeprom-1 control register (ee1cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 $fe1f eeprom-1 array configuration register (ee1acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of ee1nvr ($fe1c) 1. nonvolatile eeprom register; write by programming. = unimplemented r = rese rved unused = unused figure 6-1. eeprom-1 register summary functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 73 6.4 functional description the 512 bytes of eeprom-1 are located at $0800-$09 ff and can be programmed or erased without an additional external high voltage supply. the program and erase operations are enabled through the use of an internal charge pump. for each byte of eepr om, the write/erase endur ance is 10,000 cycles. 6.4.1 eeprom-1 configuration the 8-bit eeprom-1 nonvolatile register ( ee1nvr) and the 16-bit eeprom-1 timebase divider nonvolatile register (ee1divnvr) contain the default settings for th e following eeprom configurations: ? eeprom-1 timebase reference ? eeprom-1 security option ? eeprom-1 block protection ee1nvr and ee1divnvr are nonvolatile eeprom regist ers. they are programmed and erased in the same way as eeprom bytes. the contents of these r egisters are loaded into their respective volatile registers during a mcu reset. the values in these read/write volatile registers define the eeprom-1 configurations. for ee1nvr, the corresponding volatile register is the eeprom-1 array configuration register (ee1acr). for the ee1divncr (two 8-bit registers: ee1divhnvr and ee1divlnvr), the corresponding volatile register is the eeprom-1 divider register (ee1div: ee1divh and ee1 divl). 6.4.2 eeprom-1 ti mebase requirements a 35 s timebase is required by the eeprom-1 control ci rcuit for program and er ase of eeprom content. this timebase is derived from dividing the cgmxcl k or bus clock (selecte d by eedivclk bit in config-2 register) using a timebase divider circ uit controlled by the 16 -bit eeprom-1 timebase divider ee1div register (ee1divh and ee1divl). as the cgmxclk or bus clock is user selected, the eeprom-1 timebase di vider register must be configured with the appropriate value to obtain the 35 s. the timebase divider value is calculated by using the following formula: ee1div= int[reference frequency(hz) x 35 x10 -6 +0.5] this value is written to the eeprom-1 timeba se divider register (ee1divh and ee1divl) or programmed into the eeprom-1 tim ebase divider nonvolatile register prior to any eeprom program or erase operations ( 6.4.1 eeprom-1 configuration and 6.4.2 eeprom-1 timebase requirements ). eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 74 freescale semiconductor 6.4.3 eeprom-1 prog ram/erase protection the eeprom has a special feature that designates the 16 bytes of addresses from $08f0 to $08ff to be permanently secured. this program/erase protect option is enabled by programming the eeprtct bit in the eeprom-1 nonvolatile register (ee1nvr) to a logic zero. once the eeprtct bit is program med to 0 for the first time: ? programming and erasing of secured locations $08f0 to $08ff is permanently disabled. ? secured locations $08f0 to $08ff can be read as normal. ? programming and erasing of ee1nvr is permanently disabled. ? bulk and block erase operations are disabled for the unprotected locations $0800-$08ef, $0900-$09ff. ? single byte program and erase operations are still available for locations $0800-$08ef and $0900-$09ff for all bytes that are not protected by the eeprom-1 block protect eebpx bits (see 6.4.4 eeprom-1 block protection and 6.5.2 eeprom-1 array configuration register ) note once armed, the protect option is permanently enabled. as a consequence, all functions in the ee1nvr will re main in the state they were in immediately before the security was enabled. 6.4.4 eeprom-1 block protection the 512 bytes of eeprom-1 ar e divided into four 128-byte blocks. ea ch of these blocks can be protected from erase/program operations by se tting the eebpx bit in the ee1nvr. table 6-1 shows the address ranges for the blocks. these bits are effective after a reset or a upon read of the ee1nvr register. the block protect configuration can be modified by erasing/programmi ng the corresponding bits in the ee1nvr register and then reading the ee1nvr register. please see 6.5.2 eeprom-1 array configuration register for more information. note once eedivsecd in the ee1divhnvr is programmed to 0 and after a system reset, the ee1div security feature is permanently enabled because the eedivsecd bit in the ee1divh is always loaded with 0 thereafter. once this security feature is armed, erase and program mode are disabled for ee1divhnvr and ee1divlnvr. modifications to the ee1divh and ee1divl registers are also disabled. therefore, be cautious on programming a value into the ee1divhnvr. table 6-1. eeprom-1 array address blocks block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 75 6.4.5 eeprom-1 prog ramming and erasing the unprogrammed or erase state of an eeprom bit is a logic 1. the factory default for all bytes within the eeprom-1 array is $ff. the programming operation changes an eepr om bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). in a single programming operation, the minimum eeprom programming size is one bit; the maximum is eight bits (one byte). the erase operation changes an eeprom bit from logic 0 to logic 1. in a single eras e operation, the minimum eeprom erase size is one byte; t he maximum is the entire eeprom-1 array. the eeprom can be programmed such that one or multiple bits are programmed (written to a logic 0) at a time. however, the user may never program the same bit location more than once before erasing the entire byte. in other words, the user is not allowed to program a logic 0 to a bit that is already programmed (bit state is already logic 0). for some applications it might be advantageous to track more than 10k events with a single byte of eeprom by programming one bit at a time. for that purpose, a special selective bit programming technique is available. an example of this technique is illustrated in table 6-2 . note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. when this technique is utilized, a program/erase cycl e is defined as multiple program sequences (up to eight) to a unique location followe d by a single erase operation. 6.4.5.1 program/erase using auto bit an additional feature available fo r eeprom-1 program and erase oper ations is the auto mode. when enabled, auto mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the eepgm bit. please see 6.4.5.2 eeprom-1 programming , 6.4.5.3 eeprom-1 erasing , and 6.5.1 eeprom-1 control register for more information. table 6-2. example selective bit programming description description program data in binary result in binary original state of byte (erased) n/a 1111:1111 first event is recorded by programm ing bit position 0 1111:1110 1111:1110 second event is recorded by programming bit position 1 1111:1101 1111:1100 third event is recorded by programm ing bit position 2 1111:1011 1111:1000 fourth event is recorded by programming bit position 3 1111:0111 1111:0000 events five through eight are recorded in a similar fashion eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 76 freescale semiconductor 6.4.5.2 eeprom-1 programming the unprogrammed or erase state of an eeprom bit is a logic 1. programming changes the state to a logic 0. only eeprom bytes in the non-protected blocks and the ee1nvr register can be programmed. use the following procedure to program a byte of eeprom: 1. clear eeras1 and eeras0 and set eelat in the ee1cr. (a) note if using the auto mode, also set the auto bit during step 1. 2. write the desired data to the desired eeprom address. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for time, t eefpv , for the programming voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. eeras1 and eeras0 must be cleared for programming. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom-1 address will be latched. if eelat is set, other writes to the ee1cr will be allowed after a valid eeprom-1 write. b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom-1 locations other than the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom-1 locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eepgm . however, on other mcus, this delay time may be different. for forward compatibility, softwar e should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom-1 array. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 77 6.4.5.3 eeprom-1 erasing the programmed state of an eeprom bit is logic 0. erasing changes the state to a logic 1. only eeprom-1 bytes in the non-protected blocks and the ee1nvr register can be erased. use the following procedure to erase a byte , block or the entire eeprom-1 array: 1. configure eeras1 and eeras0 for byte, block or bulk erase; set eelat in ee1cr. (a) note if using the auto mode, also set the auto bit in step 1. 2. byte erase: write any data to the desired address. (b) block erase: write any data to an address within the desired block. (b) bulk erase: write any data to an address within the array. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time: t eebyte for byte erase; t eeblock for block erase; t eebulk. for bulk erase. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the erasing voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. setting the eelat bit configures t he address and data buses to latch data for erasing the array. only va lid eeprom-1 addresses will be latched. if eelat is set, other writes to the ee1cr will be allowed after a valid eeprom-1 write. b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom-1 locations other than the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom-1 locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eebyte /t eeblock /t eebulk . however, on other mcus, this delay time may be different. for forward compat ibility, software should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom-1 array. eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 78 freescale semiconductor 6.5 eeprom-1 register descriptions four i/o registers and three nonvol atile registers control program, er ase and options of the eeprom-1 array. 6.5.1 eeprom-1 co ntrol register this read/write register controls programming/erasing of the array. bit 7? unused bit this read/write bit is software programmable but has no functionality. eeoff ? eeprom-1 power down this read/write bit disables t he eeprom-1 module for lower power consumption. any attempts to access the array will give unpredict able results. reset clears this bit. 1 = disable eeprom-1 array 0 = enable eeprom-1 array eeras1 and eeras0 ? erase/program mode select bits these read/write bits set the eras e modes. reset clears these bits. eelat ? eeprom-1 latch control this read/write bit latches the address and data buses for programming the eeprom-1 array. eelat cannot be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom-1 programming or erase operation 0 = buses configured for normal operation address: $fe1d bit 7654321bit 0 read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 = unimplemented figure 6-2. eeprom-1 control register (ee1cr) table 6-3. eeprom-1 program/erase mode select eebpx eeras1 eeras0 mode 0 0 0 byte program 0 0 1 byte erase 010block erase 0 1 1 bulk erase 1 x x no erase/program x = don?t care eeprom-1 register descriptions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 79 auto ? automatic termination of program/erase cycle when auto is set, eepgm is cleared automatically a fter the program/erase cy cle is terminated by the internal timer. (see note d for 6.4.5.2 eeprom-1 programming , 6.4.5.3 eeprom-1 erasing , and 28.1.13 eeprom memory characteristics ) 1 = automatic clear of eepgm is enabled 0 = automatic clear of eepgm is disabled eepgm ? eeprom-1 program/erase enable this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom-1 array if the eelat bit is set and a wr ite to a valid eeprom-1 location has occurred. reset clears the eepgm bit. 1 = eeprom-1 programming/erasing power switched on 0 = eeprom-1 programming/erasing power switched off note writing logic 0s to both the eelat and eepgm bits with a single instruction will clear eepgm only to allow time for the removal of high voltage. 6.5.2 eeprom-1 array configuration register the eeprom-1 array configurati on register configures eeprom-1 security and eeprom-1 block protection. this read-only register is loaded with the contents of the eeprom-1 nonvolatile register (ee1nvr) after a reset. bit 7:5 ? unused bits these read/write bits are software programmable but have no functionality. eeprtct ? eeprom-1 protection bit the eeprtct bit is used to enable the security feature in the eeprom (see eeprom-1 program/erase protection). 1 = eeprom-1 security disabled 0 = eeprom-1 security enabled this feature is a write-once feature. once the protection is enabled it may not be disabled. address: $fe1f bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of ee1nvr ($fe1c) = unimplemented figure 6-3. eeprom-1 array configuration register (ee1acr) eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 80 freescale semiconductor eebp[3:0] ? eeprom-1 block protection bits these bits prevent blocks of eeprom-1 array from being programmed or erased. 1 = eeprom-1 array block is protected 0 = eeprom-1 array block is unprotected block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff table 6-4. eeprom-1 block protect and security summary address range eebpx eeprtct = 1 eeprtct = 0 $0800 - $087f eebp0 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp0 = 1 protected protected $0880 - $08ef eebp1 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp1 = 1 protected protected $08f0 - $08ff eebp1 = 0 byte programming available bulk, block and byte erasing available secured (no programming or erasing) eebp1 = 1 protected $0900 - $097f eebp2 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp2 = 1 protected protected $0980 - $09ff eebp3 = 0 byte programming available bulk, block and byte available byte programming available only byte erasing available eebp3 = 1 protected protected eeprom-1 register descriptions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 81 6.5.3 eeprom-1 no nvolatile register the contents of this register is loaded into the eepr om-1 array configuration register (ee1acr) after a reset. this register is erased an d programmed in the same way as an eeprom byte. (see 6.5.1 eeprom-1 control register for individual bit descriptions). note the ee1nvr will leave the factory programmed with $f0 such that the full array is available and unprotected. 6.5.4 eeprom-1 tim ebase divider register the 16-bit eeprom-1 timebase divider register cons ists of two 8-bit registers: ee1divh and ee1divl. the 11-bit value in this register is used to c onfigure the timebase divider circuit to obtain the 35 s timebase for eeprom-1 control. these two read/write registers are respectively lo aded with the contents of the eeprom-1 timebase divider nonvolatile registers (ee1divhnvr and ee1divlnvr) after a reset. address: $fe1c bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: pv pv = programmed value or 1 in the erased state. figure 6-4. eeprom-1 nonvolatile register (ee1nvr) address: $fe1a bit 7 6 5 4 3 2 1 bit 0 read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: reset: contents of ee1divhnvr ($fe10), bits [6:3] = 0 = unimplemented figure 6-5. ee1div divider high register (ee1divh) address: $fe1b bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of ee1divlnvr ($fe11) figure 6-6. ee1div divider low register (ee1divl) eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 82 freescale semiconductor eedivsecd ? eeprom-1 divider security disable this bit enables/disables the security feature of the ee1div registers. when ee1div security feature is enabled, the state of the registers ee1divh and ee1divl are locked (including eedivsecd bit). the ee1divhnvr and ee1divlnvr nonvolatile memory registers are also protected from being erased/programmed. 1 = ee1div security feature disabled 0 = ee1div security feature enabled eediv[10:0] ? eeprom-1 timebase prescaler these prescaler bits store the value of ee1div whic h is used as the divisor to derive a timebase of 35 s from the selected reference clock source (cgmxclk or bus block in the config-2 register) for the eeprom-1 related internal timer and circuits. eediv[10:0] bits are readable at any time. they are writable when eelat = 0 and eedivsecd = 1. the ee1div value is calculated by the following formula: ee1div= int[reference frequency(hz) x 35 x10 -6 +0.5] where the result inside the bracket is rounded down to the nearest integer value for example, if the reference frequency is 4.9152mhz, the ee1div value is 172 note programming/erasing the eeprom with an improper ee1div value may result in data lost and reduc e endurance of the eeprom device. 6.5.5 eeprom-1 timebase di vider nonvolatile register the 16-bit eeprom-1 timebase divider nonvolatile regi ster consists of two 8-bit registers: ee1divhnvr and ee1divlnvr. the contents of these two regist ers are respectively l oaded into the eeprom-1 timebase divider registers, ee1divh and ee1divl, after a reset. these two registers are erased and programmed in the same way as an eeprom-1 byte. address: $fe10 bit 7 6 5 4 3 2 1 bit 0 read: eedivs- ecd r r r r eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank r=reserved figure 6-7. eeprom-1 divider nonvolatile register high (ee1divhnvr)) address: $fe11 bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank figure 6-8. eeprom-1 divider nonv olatile register low (ee1divlnvr) low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 83 these two registers are protected from erase and progr am operations if the eedivsecd is set to logic 1 in the ee1divh (see eeprom-1 timebase divider register) or programmed to a logic 1 in the ee1divhnvr. note once eedivsecd in the ee1divhnvr is programmed to 0 and after a system reset, the ee1div security feature is permanently enabled because the eedivsecd bit in the ee1divh is always loaded with 0 thereafter. once this security feature is armed, erase and program mode are disabled for ee1divhnvr and ee1divlnvr. modifications to the ee1divh and ee1divl registers are also disabled. therefore, care should be taken before programming a value into the ee1divhnvr. 6.6 low-power modes the wait and stop instructions can put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction does not affect the eeprom. it is possible to start the program or erase sequence on the eeprom and put the mcu in wait mode. 6.6.2 stop mode the stop instruction reduces t he eeprom power consumption to a minimum. the stop instruction should not be executed while a programm ing or erasing sequence is in progress. if stop mode is entered while eelat and eepgm ar e set, the programming sequence will be stopped and the programming voltage to the eeprom arra y removed. the programming sequence will be restarted after leaving stop mode; access to the eeprom is only possible after the programming sequence has completed. if stop mode is entered while eelat and eepgm is cleared, the programming sequence will be terminated abruptly. in either case, the data integrity of the eeprom is not guaranteed. eeprom-1 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 84 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 85 chapter 7 eeprom-2 memory 7.1 introduction this chapter describes the 512 bytes of electr ically erasable programmable read-only memory (eeprom) residing at address r ange $0600 to $07ff. there are 1 024 bytes of eeprom available on the mc68hc908as60a and mc68hc908az60a which are physically located in two 512 byte arrays. for information relating to the array coveri ng address range $0800 to $09ff please see chapter 6 eeprom-1 memory . 7.2 features features of the eeprom-2 include the following: ? 512 bytes nonvolatile memory ? byte, block, or bulk erasable ? nonvolatile eeprom configurati on and block protection options ? on-chip charge pump for programming/erasing ? security option ? auto bit driven programming/erasing time feature 7.3 eeprom-2 register summary the eeprom-2 register summary is shown in figure 7-1 . eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 86 freescale semiconductor addr.register name bit 7654321bit 0 $ff70 ee2div nonvolatile register high (ee2divhnvr)* read: eedivs- ecd rrrreediv10eediv9eediv8 write: reset: unaffected by reset; $ff when blank $ff71 ee2div nonvolatile register low (ee2divlnvr)* read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank $ff7a ee2 divider register high (ee2divh) read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: reset: contents of ee2divhnvr ($ff70); bits[6:3] = 0 $ff7b ee2 divider register low (ee2divl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of ee2divlnvr ($ff71) $ff7c eeprom-2 nonvolatile register (ee2nvr)* read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $f0 $ff7d eeprom-2 control register (ee2cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 $ff7f eeprom-2 array configuration register (ee2acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of ee2nvr ($ff7c) * nonvolatile eeprom regist er; write by programming. = unimplemented r = rese rved unused = unused figure 7-1. eeprom-2 register summary functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 87 7.4 functional description the 512 bytes of eeprom-2 are located at $0600-$07 ff and can be programmed or erased without an additional external high voltage supply. the program and erase operations are enabled through the use of an internal charge pump. for each byte of eepr om, the write/erase endur ance is 10,000 cycles. 7.4.1 eeprom-2 configuration the 8-bit eeprom-2 nonvolatile register ( ee2nvr) and the 16-bit eeprom-2 timebase divider nonvolatile register (ee2divnvr) contain the default settings for th e following eeprom configurations: ? eeprom-2 timebase reference ? eeprom-2 security option ? eeprom-2 block protection ee2nvr and ee2divnvr are nonvolatile eeprom regist ers. they are programmed and erased in the same way as eeprom bytes. the contents of these r egisters are loaded into their respective volatile registers during a mcu reset. the values in these read/write volatile registers define the eeprom-2 configurations. for ee2nvr, the corresponding volatile register is the eeprom-2 array configuration register (ee2acr). for the ee2divncr (two 8-bit registers: ee2divhnvr and ee2divlnvr), the corresponding volatile register is the eeprom-2 divider register (ee2div: ee2divh and ee2 divl). 7.4.2 eeprom-2 ti mebase requirements a 35 s timebase is required by the eeprom-2 control ci rcuit for program and er ase of eeprom content. this timebase is derived from dividing the cgmxcl k or bus clock (selecte d by eedivclk bit in config-2 register) using a timebase divider circ uit controlled by the 16 -bit eeprom-2 timebase divider ee2div register (ee2divh and ee2divl). as the cgmxclk or bus clock is user selected, the eeprom-2 timebase di vider register must be configured with the appropriate value to obtain the 35 s. the timebase divider value is calculated by using the following formula: ee2div= int[reference frequency(hz) x 35 x10 -6 +0.5] this value is written to the eeprom-2 timeba se divider register (ee2divh and ee2divl) or programmed into the eeprom-2 tim ebase divider nonvolatile register prior to any eeprom program or erase operations ( 7.4.1 eeprom-2 configuration and 7.4.2 eeprom-2 timebase requirements ). eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 88 freescale semiconductor 7.4.3 eeprom-2 prog ram/erase protection the eeprom has a special feature that designates the 16 bytes of addresses from $06f0 to $06ff to be permanently secured. this program/erase protect option is enabled by programming the eeprtct bit in the eeprom-2 nonvolatile register (ee2nvr) to a logic zero. once the eeprtct bit is program med to 0 for the first time: ? programming and erasing of secured locations $06f0 to $06ff is permanently disabled. ? secured locations $06f0 to $06ff can be read as normal. ? programming and erasing of ee2nvr is permanently disabled. ? bulk and block erase operations are disabled for the unprotected locations $0600-$06ef, $0700-$07ff. ? single byte program and erase operations are still available for locations $0600-$06ef and $0700-$07ff for all bytes that are not protected by the eeprom-2 block protect eebpx bits (see 7.4.4 eeprom-2 block protection and 7.5.2 eeprom-2 array configuration register ) note once armed, the protect option is permanently enabled. as a consequence, all functions in the ee2nvr will re main in the state they were in immediately before the security was enabled. 7.4.4 eeprom-2 block protection the 512 bytes of eeprom-2 ar e divided into four 128-byte blocks. ea ch of these blocks can be protected from erase/program operations by se tting the eebpx bit in the ee2nvr. table 7-1 shows the address ranges for the blocks. these bits are effective after a reset or a upon read of the ee2nvr register. the block protect configuration can be modified by erasing/programmi ng the corresponding bits in the ee2nvr register and then reading the ee2nvr register. please see 7.5.2 eeprom-2 array configuration register for more information. note once eedivsecd in the ee2divhnvr is programmed to 0 and after a system reset, the ee2div security feature is permanently enabled because the eedivsecd bit in the ee2divh is always loaded with 0 thereafter. once this security feature is armed, erase and program mode are disabled for ee2divhnvr and ee2divlnvr. modifications to the ee2divh and ee2divl registers are also disabled. therefore, be cautious on programming a value into the ee2divhnvr. table 7-1. eeprom-2 array address blocks block number (eebpx) address range eebp0 $0600?$067f eebp1 $0680?$06ff eebp2 $0700?$077f eebp3 $0780?$07ff functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 89 7.4.5 eeprom-2 prog ramming and erasing the unprogrammed or erase state of an eeprom bit is a logic 1. the factory default for all bytes within the eeprom-2 array is $ff. the programming operation changes an eepr om bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). in a single programming operation, the minimum eeprom programming size is one bit; the maximum is eight bits (one byte). the erase operation changes an eeprom bit from logic 0 to logic 1. in a single eras e operation, the minimum eeprom erase size is one byte; t he maximum is the entire eeprom-2 array. the eeprom can be programmed such that one or multiple bits are programmed (written to a logic 0) at a time. however, the user may never program the same bit location more than once before erasing the entire byte. in other words, the user is not allowed to program a logic 0 to a bit that is already programmed (bit state is already logic 0). for some applications it might be advantageous to track more than 10k events with a single byte of eeprom by programming one bit at a time. for that purpose, a special selective bit programming technique is available. an example of this technique is illustrated in table 7-2 . note none of the bit locations are actual ly programmed more than once although the byte was programmed eight times. when this technique is utilized, a program/erase cycl e is defined as multiple program sequences (up to eight) to a unique location followe d by a single erase operation. 7.4.5.1 program/erase using auto bit an additional feature available fo r eeprom-2 program and erase oper ations is the auto mode. when enabled, auto mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the eepgm bit. please see 7.4.5.2 eeprom-2 programming , 7.4.5.3 eeprom-2 erasing , and 7.5.1 eeprom-2 control register for more information. table 7-2. example selective bit programming description description program data in binary result in binary original state of byte (erased) n/a 1111:1111 first event is recorded by programm ing bit position 0 1111:1110 1111:1110 second event is recorded by programming bit position 1 1111:1101 1111:1100 third event is recorded by programm ing bit position 2 1111:1011 1111:1000 fourth event is recorded by programming bit position 3 1111:0111 1111:0000 events five through eight are recorded in a similar fashion eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 90 freescale semiconductor 7.4.5.2 eeprom-2 programming the unprogrammed or erase state of an eeprom bit is a logic 1. programming changes the state to a logic 0. only eeprom bytes in the non-protected blocks and the ee2nvr register can be programmed. use the following procedure to program a byte of eeprom: 1. clear eeras1 and eeras0 and set eelat in the ee2cr. (a) note if using the auto mode, also set the auto bit during step 1. 2. write the desired data to the desired eeprom address. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for time, t eefpv , for the programming voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. eeras1 and eeras0 must be cleared for programming. setting the eelat bit configures the address and data buses to latch data for programming the array. only data with a valid eeprom-2 address will be latched. if eelat is set, other writes to the ee2cr will be allowed after a valid eeprom-2 write. b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom-2 locations other than the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom-2 locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eepgm . however, on other mcus, this delay time may be different. for forward compatibility, softwar e should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom-2 array. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 91 7.4.5.3 eeprom-2 erasing the programmed state of an eeprom bit is logic 0. erasing changes the state to a logic 1. only eeprom-2 bytes in the non-protected blocks and the ee2nvr register can be erased. use the following procedure to erase a byte , block or the entire eeprom-2 array: 1. configure eeras1 and eeras0 for byte, block or bulk erase; set eelat in ee2cr. (a) note if using the auto mode, also set the auto bit in step 1. 2. byte erase: write any data to the desired address. (b) block erase: write any data to an address within the desired block. (b) bulk erase: write any data to an address within the array. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time: t eebyte for byte erase; t eeblock for block erase; t eebulk. for bulk erase. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the erasing voltage to fall. go to step 8. 7. poll the eepgm bit until it is cleared by the internal timer. (d) 8. clear eelat bits. (e) note a. setting the eelat bit configures t he address and data buses to latch data for erasing the array. only va lid eeprom-2 addresses will be latched. if eelat is set, other writes to the ee2cr will be allowed after a valid eeprom-2 write. b. if more than one valid eeprom write occurs, the last address and data will be latched overriding the previous address and data. once data is written to the desired address, do not read eeprom-2 locations other than the written location. (reading an eeprom location returns the latched data and causes the read address to be latched). c. the eepgm bit cannot be set if the eelat bit is cleared or a non-valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not read any eeprom-2 locations; otherwise, the current program cy cle will be unsuccessful. when eepgm is set, the on-board programming sequence will be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t eebyte /t eeblock /t eebulk . however, on other mcus, this delay time may be different. for forward compat ibility, software should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only clear eepgm. this is to allow time for removal of high voltage from the eeprom-2 array. eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 92 freescale semiconductor 7.5 eeprom-2 register descriptions four i/o registers and three nonvol atile registers control program, er ase and options of the eeprom-2 array. 7.5.1 eeprom-2 co ntrol register this read/write register controls programming/erasing of the array. bit 7? unused bit this read/write bit is software programmable but has no functionality. eeoff ? eeprom-2 power down this read/write bit disables t he eeprom-2 module for lower power consumption. any attempts to access the array will give unpredict able results. reset clears this bit. 1 = disable eeprom-2 array 0 = enable eeprom-2 array eeras1 and eeras0 ? erase/program mode select bits these read/write bits set the eras e modes. reset clears these bits. eelat ? eeprom-2 latch control this read/write bit latches the address and data buses for programming the eeprom-2 array. eelat cannot be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom-2 programming or erase operation 0 = buses configured for normal operation address: $ff7d bit 7654321bit 0 read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 = unimplemented figure 7-2. eeprom-2 control register (ee2cr) table 7-3. eeprom-2 program/erase mode select eebpx eeras1 eeras0 mode 0 0 0 byte program 0 0 1 byte erase 010block erase 0 1 1 bulk erase 1 x x no erase/program x = don?t care eeprom-2 register descriptions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 93 auto ? automatic termination of program/erase cycle when auto is set, eepgm is cleared automatically a fter the program/erase cy cle is terminated by the internal timer. (see note d for 7.4.5.2 eeprom-2 programming , 7.4.5.3 eeprom-2 erasing , and 28.1.13 eeprom memory characteristics ) 1 = automatic clear of eepgm is enabled 0 = automatic clear of eepgm is disabled eepgm ? eeprom-2 program/erase enable this read/write bit enables the internal charge pump and applies the programming/erasing voltage to the eeprom-2 array if the eelat bit is set and a wr ite to a valid eeprom-2 location has occurred. reset clears the eepgm bit. 1 = eeprom-2 programming/erasing power switched on 0 = eeprom-2 programming/erasing power switched off note writing logic 0s to both the eelat and eepgm bits with a single instruction will clear eepgm only to allow time for the removal of high voltage. 7.5.2 eeprom-2 array configuration register the eeprom-2 array configurati on register configures eeprom-2 security and eeprom-2 block protection. this read-only register is loaded with the contents of the eeprom-2 nonvolatile register (ee2nvr) after a reset. bit 7:5 ? unused bits these read/write bits are software programmable but have no functionality. eeprtct ? eeprom-2 protection bit the eeprtct bit is used to enable the security feature in the eeprom (see eeprom-2 program/erase protection). 1 = eeprom-2 security disabled 0 = eeprom-2 security enabled this feature is a write-once feature. once the protection is enabled it may not be disabled. address: $ff7f bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of ee2nvr ($ff7c) = unimplemented figure 7-3. eeprom-2 array configuration register (ee2acr) eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 94 freescale semiconductor eebp[3:0] ? eeprom-2 block protection bits these bits prevent blocks of eeprom-2 array from being programmed or erased. 1 = eeprom-2 array block is protected 0 = eeprom-2 array block is unprotected block number (eebpx) address range eebp0 $0600?$067f eebp1 $0680?$06ff eebp2 $0700?$077f eebp3 $0780?$07ff table 7-4. eeprom-2 block protect and security summary address range eebpx eeprtct = 1 eeprtct = 0 $0600 - $067f eebp0 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp0 = 1 protected protected $0680 - $06ef eebp1 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp1 = 1 protected protected $06f0 - $06ff eebp1 = 0 byte programming available bulk, block and byte erasing available secured (no programming or erasing) eebp1 = 1 protected $0700 - $077f eebp2 = 0 byte programming available bulk, block and byte erasing available byte programming available only byte erasing available eebp2 = 1 protected protected $0780 - $07ff eebp3 = 0 byte programming available bulk, block and byte available byte programming available only byte erasing available eebp3 = 1 protected protected eeprom-2 register descriptions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 95 7.5.3 eeprom-2 no nvolatile register the contents of this register is loaded into the eepr om-2 array configuration register (ee2acr) after a reset. this register is erased an d programmed in the same way as an eeprom byte. (see 7.5.1 eeprom-2 control register for individual bit descriptions). note the ee2nvr will leave the factory programmed with $f0 such that the full array is available and unprotected. 7.5.4 eeprom-2 tim ebase divider register the 16-bit eeprom-2 timebase divider register cons ists of two 8-bit registers: ee2divh and ee2divl. the 11-bit value in this register is used to c onfigure the timebase divider circuit to obtain the 35 s timebase for eeprom-2 control. these two read/write registers are respectively lo aded with the contents of the eeprom-2 timebase divider nonvolatile registers (ee2divhnvr and ee2divlnvr) after a reset. address: $ff7c bit 7 6 5 4 3 2 1 bit 0 read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: pv pv = programmed value or 1 in the erased state. figure 7-4. eeprom-2 nonvolatile register (ee2nvr) address: $ff7a bit 7 6 5 4 3 2 1 bit 0 read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: reset: contents of ee2divhnvr ($ff70); bits[6:3] = 0 = unimplemented figure 7-5. ee2div divider high register (ee2divh) address: $ff7b bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of ee2divlnvr ($ff71) figure 7-6. ee2div divider low register (ee2divl) eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 96 freescale semiconductor eedivsecd ? eeprom-2 divider security disable this bit enables/disables the security feature of the ee2div registers. when ee2div security feature is enabled, the state of the registers ee2divh and ee2divl are locked (including eedivsecd bit). the ee2divhnvr and ee2divlnvr nonvolatile memory registers are also protected from being erased/programmed. 1 = ee2div security feature disabled 0 = ee2div security feature enabled eediv[10:0] ? eeprom-2 timebase prescaler these prescaler bits store the value of ee2div whic h is used as the divisor to derive a timebase of 35 s from the selected reference clock source (cgmxclk or bus block in the config-2 register) for the eeprom-2 related internal timer and circuits. eediv[10:0] bits are readable at any time. they are writable when eelat = 0 and eedivsecd = 1. the ee2div value is calculated by the following formula: ee2div= int[reference frequency(hz) x 35 x10 -6 +0.5] where the result inside the bracket is rounded down to the nearest integer value for example, if the reference frequency is 4.9152mhz, the ee2div value is 172 note programming/erasing the eeprom with an improper ee2div value may result in data lost and reduc e endurance of the eeprom device. 7.5.5 eeprom-2 timebase di vider nonvolatile register the 16-bit eeprom-2 timebase divider nonvolatile regi ster consists of two 8-bit registers: ee2divhnvr and ee2divlnvr. the contents of these two regist ers are respectively l oaded into the eeprom-2 timebase divider registers, ee2divh and ee2divl, after a reset. these two registers are erased and programmed in the same way as an eeprom-2 byte. address: $ff70 bit 7 6 5 4 3 2 1 bit 0 read: eedivs- ecd r r r r eediv10 eediv9 eediv8 write: reset: unaffected by reset; $ff when blank r=reserved figure 7-7. eeprom-2 divider nonvolatile register high (ee2divhnvr)) address: $ff71 bit 7 6 5 4 3 2 1 bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank figure 7-8. eeprom-2 divider nonv olatile register low (ee2divlnvr) low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 97 these two registers are protected from erase and progr am operations if the eedivsecd is set to logic 1 in ee2divh or programmed to a logic 1 in ee2divhnvr. note once eedivsecd in the ee2divhnvr is programmed to 0 and after a system reset, the ee2div security feature is permanently enabled because the eedivsecd bit in the ee2divh is always loaded with 0 thereafter. once this security feature is armed, erase and program mode are disabled for ee2divhnvr and ee2divlnvr. modifications to the ee2divh and ee2divl registers are also disabled. therefore, care should be taken before programming a value into the ee2divhnvr. 7.6 low-power modes the wait and stop instructions can put the mcu in low power-consumption standby modes. 7.6.1 wait mode the wait instruction does not affect the eeprom. it is possible to start the program or erase sequence on the eeprom and put the mcu in wait mode. 7.6.2 stop mode the stop instruction reduces t he eeprom power consumption to a minimum. the stop instruction should not be executed while a programm ing or erasing sequence is in progress. if stop mode is entered while eelat and eepgm ar e set, the programming sequence will be stopped and the programming voltage to the eeprom arra y removed. the programming sequence will be restarted after leaving stop mode; access to the eeprom is only possible after the programming sequence has completed. if stop mode is entered while eelat and eepgm is cleared, the programming sequence will be terminated abruptly. in either case, the data integrity of the eeprom is not guaranteed. eeprom-2 memory mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 98 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 99 chapter 8 central processor unit (cpu) 8.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 8.2 features features of the cpu include: ? object code fully upward-compatible with m68hc05 family ? 16-bit stack pointer with stack manipulation instructions ? 16-bit index register with x-re gister manipulation instructions ? 8-mhz cpu internal bus frequency ? 64-kbyte program/data memory space ? 16 addressing modes ? memory-to-memory data moves without using accumulator ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? enhanced binary-coded decimal (bcd) data handling ? modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes ? low-power stop and wait modes 8.3 cpu registers figure 8-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 100 freescale semiconductor figure 8-1. cpu registers 8.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 8.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 8-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 8-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 101 8.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 8.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 8-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 8-5. program counter (pc) central processor unit (cpu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 102 freescale semiconductor 8.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 8-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 103 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 8.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 8.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 8.5.1 wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. ? disables the cpu clock 8.5.2 stop mode the stop instruction: ? clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 8.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 104 freescale semiconductor 8.7 instruction set summary table 8-1 provides a summary of the m68hc08 instruction set. table 8-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c instruction set summary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 105 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 8-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 106 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 8-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc instruction set summary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 107 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 8-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 central processor unit (cpu) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 108 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 8-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c opcode map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 109 8.8 opcode map see table 8-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 8-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 110 freescale semiconductor central processor unit (cpu) table 8-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 111 chapter 9 system integration module (sim) 9.1 introduction this chapter describes the system integration module (sim), which supports up to 32 external and/or internal interrupts. together with the central processo r unit (cpu), the sim controls all mcu activities. a block diagram of the sim is shown in figure 9-1 . figure 9-2 is a summary of the sim input/output (i/o) registers. the sim is a system state controller th at coordinates cpu and exception timing. the sim is responsible for: ? bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control ? master reset control, including power-on reset (por) and computer operating properly (cop) timeout ? interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation ? cpu enable/disable timing system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 112 freescale semiconductor figure 9-1. sim block diagram register name bit 7654321bit 0 sim break status register (sbsr) rrrrrrbwr sim reset status register (srsr) por pin cop ilop ilad 0 lvi 0 sim break flag control register (sbfcr)bcferrrrrrr r = reserved figure 9-2. sim i/o register summary table 9-1. i/o register address summary register sbsr srsr sbfcr address $fe00 $fe01 $fe03 stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 sim bus clock control and generation mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 113 table 9-2 shows the internal signal names used in this chapter. 9.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an in coming clock, cgmout, as shown in figure 9-3 . this clock can come from either an external oscillat or or from the on-chip pll. (see chapter 10 clock generator module (cgm) ). figure 9-3. cgm clock signals 9.2.1 bus timing in user mode , the internal bus frequency is either the crys tal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. (see chapter 10 clock generator module (cgm) ). table 9-2. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc3 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 114 freescale semiconductor 9.2.2 clock startup from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an i nactive phase until after 4096 cgmxclk cycles. the rst pin is driven low by the sim during this entire per iod. the bus clocks start upon completion of the timeout. 9.2.3 clocks in st op mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. see 9.6.2 stop mode . in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 9.3 reset and system initialization the mcu has these reset sources: ? power-on reset module (por) ? external reset pin (rst ) ? computer operating properly module (cop) ? low-voltage inhibit module (lvi) ? illegal opcode ? illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 9.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr) (see 9.7 sim registers ). 9.3.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl . figure 9-4 shows the relative timing. figure 9-4. external reset timing rst iab pc vect h vect l cgmout reset and system initialization mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 115 9.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 9-5 ). an internal reset can be caused by an il legal address, illegal opc ode, cop timeout, lvi, or por (see figure 9-6 ). note that for lvi or por resets, th e sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 9-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. figure 9-5. internal reset timing figure 9-6. sources of internal reset table 9-3. pin bit set timing reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 116 freescale semiconductor 9.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. another sixty-four cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: ? a por pulse is generated. ? the internal reset signal is asserted. ? the sim enables cgmout. ? internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. ?the rst pin is driven low during the oscillator stabilization time. ? the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. figure 9-7. por recovery 9.3.2.2 computer operating properly (cop) reset the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr) if the copd bit in the config-1 register is at logic zero. see chapter 15 computer operating properly (cop) . 9.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the config-1 register is logic zero, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff sim counter mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 117 9.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. warning extra care should be exercised if code in this part has been migrated from older hc08 devices since the illegal address reset specification may be different. also, extra care should be exercised when using this emulation part for development of code to be run in rom az, ab or as family parts with a smaller memory size since some legal addresses will become illegal addresses on the smaller rom memory map device and may as a result generate unwanted resets. 9.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the v lvii voltage. the lvi bit in the sim reset status register (srsr) is set and a chip reset is asserted if the lvipwrd and lvirstd bits in the config-1 register are at logic zero. the rst pin will be held low until the sim counts 4096 cgmxclk cycles after v dd rises above v lvir . another sixty-four cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. see chapter 16 low-voltage inhibit (lvi) . 9.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly mo dule (cop). the sim counter overflow supplies the clock for the cop module. the sim counter is 12 bits long and is clock ed by the falling edge of cgmxclk. 9.4.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 9.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config-1 register. if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxcl k cycles. this is ideal for appl ications using c anned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 118 freescale semiconductor 9.4.3 sim counter and reset states external reset has no effect on the sim counter. see 9.6.2 stop mode for details. the sim counter is free-running after all reset states. see 9.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 9.5 program exception control normal, sequential program execution can be changed in three different ways: ? interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) ? reset ? break interrupts 9.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing. figure 9-10 shows interrupt recovery timing. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared), see figure 9-9 . figure 9-8 . interrupt entry module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit program exception control mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 119 figure 9-9. interrupt processing no no no yes no no yes yes (as many interrupts i bit set? from reset break interrupt? i bit set? irq1 interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes as exist on chip) system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 120 freescale semiconductor figure 9-10. interrupt recovery 9.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt servic e routine, the pending interrupt is serviced before the lda instruction is executed. figure 9-11 . interrupt recognition example module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 121 the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m68hc05, m6805 and m146805 families the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 9.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 9.5.2 reset all reset sources always have higher priority than interrupts and cannot be arbitrated. 9.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. see chapter 13 break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector location. refer to t he break interrupt subsection of each module to see how each module is affected by the break state. 9.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 9.6 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 122 freescale semiconductor 9.6.1 wait mode in wait mode, the cpu clocks are inactive while one set of peripheral clocks continue to run. figure 9-12 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break wait bit, bw, in the sim break status register (sbsr ). if the cop disable bit, co pd, in the configuration register is logic 0, then the computer operating pro perly module (cop) is enabled and remains active in wait mode. figure 9-12. wait mode entry timing figure 9-13. wait recovery from interrupt or break figure 9-14. wait recovery from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 123 9.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also caus es an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is se lectable using the ssrec bit in the configuration register (config-1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal fo r applications using canned oscillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. the break module is inactive in stop mode. the stop instruction does not affect break module register states. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 9-15 shows stop mode entry timing. note to minimize stop current, all pins conf igured as inputs should be driven to a logic 1 or logic 0. figure 9-15. stop mode entry timing figure 9-16. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction . cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 124 freescale semiconductor 9.7 sim registers the sim has three memory mapped registers. 9.7.1 sim break status register the sim break status register contains a flag to i ndicate that a break caused an exit from wait mode. bw ? sim break wait this status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. clear bw by writing a 0 to it. reset clears bw. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 9.7.2 sim reset status register the srsr register contains flags that show the s ource of the last reset. the status register will automatically clear after reading it. a power-on reset sets the por bit and clears all other bits in the register. all other reset sources set the individual fl ag bits but do not clear the register. more than one reset source can be flagged at any time depending on the c onditions at the time of the internal or external reset. for example, the por and lvi bits can both be set if the power supply has a slow rise time. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr address: $fe00 bit 7654321bit 0 read: rrrrrr bw r write: see note reset: 0 r = reserved note: writing a logic 0 clears bw figure 9-17. sim break status register (sbsr) address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 = unimplemented figure 9-18. sim reset status register (srsr) sim registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 125 ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr 9.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 0 r= reserved figure 9-19. sim break flag control register (sbfcr) system integration module (sim) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 126 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 127 chapter 10 clock generator module (cgm) 10.1 introduction the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmo ut, from which the system clocks are derived. cgmout is based on either the crystal clock divide d by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequenc y generator designed for use with 1-mhz to 8-mhz crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without using high frequency crystals. 10.2 features features of the cgm include: ? phase-locked loop with output frequency in in teger multiples of the crystal reference ? programmable hardware voltage-controlled oscillator (vco) for low-jitter operation ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? cpu interrupt on entry or exit from locked condition 10.3 functional description the cgm consists of three major submodules: ? crystal oscillator circuit ? the crystal oscillat or circuit generates the constant crystal frequency clock, cgmxclk. ? phase-locked loop (pll) ? the pll generates the programmable vco frequency clock cgmvclk. ? base clock selector circuit ? this software-cont rolled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base clock, cgmout. the system clocks are derived from cgmout. figure 10-1 shows the structure of the cgm. clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 128 freescale semiconductor figure 10-1. cgm block diagram phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmvdv cgmvclk interrupt control cgmint cgmrdv pll analog cgmrclk select circuit lock auto acq vrs7?vrs4 pllie pllf mul7?mul4 v dda cgmxfc v ss osc1 cgmxclk ptc3 monitor mode bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 129 10.3.1 crystal os cillator circuit the crystal oscillator circuit consists of an inverting am plifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the out put. the simoscen signal enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to pr oduce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on ex ternal factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal osci llator circuit. connect the external clock to the osc1 pin and let the osc2 pin float. 10.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. register name bit 7654321bit 0 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 pll bandwidth control register (pb- wc) read: auto lock acq xld 0000 write: reset:00000000 pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 = unimplemented figure 10-2. i/o register summary table 10-1. i/o register address summary register pctl pbwc ppg address $001c $001d $001e clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 130 freescale semiconductor 10.3.2.1 circuits the pll consists of these circuits: ? voltage-controlled oscillator (vco) ? modulo vco frequency divider ? phase detector ? loop filter ? lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, incl uding supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f cgmvrs . modulating the voltage on the cgmxfc pin changes the frequency wi thin this range. by design, f cgmvrs is equal to the nominal center-of-range frequency, f nom , (4.9152 mhz) times a linear factor l or (l)f nom . cgmrclk is the pll reference clock, a buffered ve rsion of cgmxclk. cgmrclk runs at a frequency, f cgmrclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency f cgmrdv =f cgmrclk . the vco?s output clock, cgmvclk, running at a frequency f cgmvclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor, n. the divider?s output is the vco feedback clock, cgmvdv, running at a frequency f cgmvdv =f cgmvclk /n. 10.3.2.4 programming the pll for more information. the phase detector then compares the vco feedback cloc k, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor c onnected to cgmxfc based on the width and direction of the correction pulse. the fi lter can make fast or slow corrections depending on its mode, as described in 10.3.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f cgmrdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 10.3.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: ? acquisition mode ? in acquisition mode, the filt er can make large frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired freq uency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. see 10.5.2 pll bandwidth control register . ? tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see 10.3.3 base clock selector circuit . the pll is automatically in tracking mode when it?s not in acquisition mode or when the acq bit is set. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 131 10.3.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manua lly or automatically. in automatic bandwidth control mode (auto = 1), th e lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is used to determine when the vco clock, cgmvclk, is safe to use as th e source for the base clock, cgmout. see 10.5.2 pll bandwidth control register . if pll cpu interrupt requests are enabled, the software can wait for a pll cpu interrupt request and then check the lock bit. if cpu interrupts are disabled, software can poll the lock bit continuously (during pll startup, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to us e as the source for the base clock. see 10.3.3 base clock selector circuit . if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. see 10.6 interrupts . these conditions apply when the pll is in automatic bandwidth control mode: ?the acq bit (see 10.5.2 pll bandwidth control register .) is a read-only indicator of the mode of the filter. see 10.3.2.2 acquisition and tracking modes . ?the acq bit is set when the vco frequency is within a certain tolerance, trk , and is cleared when the vco frequency is out of a certain tolerance, unt . see chapter 28 electrical specifications . ? the lock bit is a read-only indica tor of the locked state of the pll. ? the lock bit is set when the vco freq uency is within a certain tolerance, lock , and is cleared when the vco frequency is out of a certain tolerance, unl . see chapter 28 electrical specifications . ? cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock c ondition changes, toggling the lock bit. see 10.5.1 pll control register . the pll also can operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. the followi ng conditions apply wh en in manual mode: ?acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. ? before entering tracking mode (acq = 1), software must wait a given time, t acq (see chapter 28 electrical specifications ), after turning on the pll by setting pllon in the pll control register (pctl). ? software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). ? the lock bit is disabled. ? cpu interrupts from the cgm are disabled. clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 132 freescale semiconductor 10.3.2.4 programming the pll use this 9-step procedure to program the pll. table 10-2 lists the variables used and their meaning (please also reference figure 10-1 ). 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . example: f vclkdes = 4 f busdes f vclkdes = 4 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. round the result to the nearest integer. example: 4. calculate the vco frequency, f cgmvclk . example: f cgmvclk = 8 4 mhz = 32 mhz 5. calculate the bus frequency, f bus , and compare f bus with f busdes . example: 6. if the calculated f bus is not within the tolerance limits of your application, select another f busdes or another f rclk . table 10-2. variable definitions variable definition f busdes desired bus clock frequency f vclkdes desired vco clock frequency f cgmrclk chosen reference crystal frequency f cgmvclk calculated vco clock frequency f bus calculated bus clock frequency f nom nominal vco center frequency f cgmvrs shifted vco center frequency n f vclkdes f cgmrclk ------------- ------------ = n 32 mhz 4 mhz -------------------- =8 = f cgmvclk nf cgmrclk = f bus f cgmvclk 4 --------------- -------- - = f bus 32 mhz 4 -------------------- =8 mhz = functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 133 7. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. example: 8. calculate the vco center-of-range frequency, f cgmvrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f cgmvrs = l f nom example: f cgmvrs = 7 4.9152 mhz = 34.4 mhz note for proper operation,. exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 9. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. 10.3.2.5 special programming exceptions the programming method described in 10.3.2.4 programming the pll , does not account for two possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: ? a 0 value for n is interpreted the same as a value of 1. ? a 0 value for l disables the pll and prevents its selection as the source for the base clock. see 10.3.3 base clock selector circuit . 10.3.3 base clock selector circuit this circuit is used to select either the crystal cl ock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input cl ocks go through a transition c ontrol circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the outpu t of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus cl ock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the l round f cgmvclk f nom ------------- ---------- - ?? ?? = l 32 mhz 4.9152 mhz --------------- ---------------- - = 7 = f cgmvrs f cgmvclk ? f nom 2 ---------------- clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 134 freescale semiconductor factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crysta l clock would be forced as the source of the base clock. 10.3.4 cgm external connections in its typical configuration, the cgm requires seven ex ternal components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator confi guration, as shown in figure 10-3 . figure 10-3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: ?crystal, x 1 ? fixed capacitor, c 1 ? tuning capacitor, c 2 (can also be a fixed capacitor) ? feedback resistor, r b ? series resistor, r s (optional) the series resistor (r s ) may not be required for all ranges of o peration, especially with high-frequency crystals. refer to the crystal manufacturer?s data for more information. figure 10-3 also shows the external components for the pll: ? bypass capacitor, c byp ? filter capacitor, c f routing should be done with great care to mi nimize signal cross talk and noise. (see 10.9 acquisition/lock time specifications for routing information and more information on the filter capacitor?s value and its effects on pll performance). figure 10-3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp *r s can be 0 (shorted) when used with higher-frequency crystals. refer to manufacturer?s data. osc1 osc2 v ss cgmxfc v dd v dda i/o signals mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 135 10.4 i/o signals the following paragraphs describe the cgm input/output (i/o) signals. 10.4.1 crystal amplif ier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 10.4.2 crystal amplif ier output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. 10.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filt er out phase corrections. a sm all external capacitor is connected to this pin. note to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible with minimum routing distances and no routing of other signals across the c f connection. 10.4.4 analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 10.4.5 oscillator e nable signal (simoscen) the simoscen signal enables the oscillator and pll. 10.4.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f cgmxclk ) and comes directly from the crystal oscillator circuit. figure 10-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 10.4.7 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signa l is used to generate the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 10.4.8 cgm cpu interrupt (cgmint) cgmint is the cpu interrupt signal generated by the pll lock detector. clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 136 freescale semiconductor 10.5 cgm registers three registers control and monitor operation of the cgm: ? pll control register (pctl) ? pll bandwidth control register (pbwc) ? pll programming register (ppg) 10.5.1 pll control register the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate a cpu interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll cpu interrupt requests enabled 0 = pll cpu interrupt requests disabled pllf ? pll flag bit this read-only bit is set whenever the lock bit toggles. pllf generates a cpu interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by readi ng the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note do not inadvertently clear the pllf bit. be aware that any read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). see 10.3.3 base clock selector circuit . reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output , cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, address: $001c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: reset:00101111 = unimplemented figure 10-4. pll control register (pctl) cgm registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 137 it may take up to three cgmxclk and three cgmv clk cycles to complete the transition from one source clock to the other. during the trans ition, cgmout is held in stasis. see 10.3.3 base clock selector circuit . reset and the stop instruction clear the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note pllon and bcs have built-in protecti on that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is cl ear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. see 10.3.3 base clock selector circuit . pctl3?pctl0 ? unimplemented these bits provide no function and always read as logic 1s. 10.5.2 pll bandwidth control register the pll bandwidth control register: ? selects automatic or manual (softw are-controlled) bandwidth control mode ? indicates when the pll is locked ? in automatic bandwidth control mode, indicates wh en the pll is in acquisition or tracking mode ? in manual operation, forces the pll into acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit selects automatic or manual b andwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. address: $001d bit 7654321bit 0 read: auto lock acq xld 0000 write: reset:00000000 = unimplemented figure 10-5. pll bandwidth control register (pbwc) clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 138 freescale semiconductor in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit ca n indicate whether the crystal reference frequency is active or not. 1 = crystal reference not active 0 = crystal reference active to check the status of the crystal reference, do the following: 1. write a 1 to xld. 2. wait n 4 cycles. n is the vco frequency multiplier. 3. read xld. the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as logic 0. bits 3?0 ? reserved for test these bits enable test functions not available in us er mode. to ensure software portability from development systems to user applications, software sh ould write 0s to bits 3?0 when writing to pbwc. 10.5.3 pll programming register the pll programming register contains the progra mming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul7?mul4 ? multiplier select bits these read/write bits control the modulo feedback di vider that selects the vco frequency multiplier, n. (see 10.3.2.1 circuits and 10.3.2.4 programming the pll ). a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a va lue of $1. reset initializes these bits to $6 to give a default multiply value of 6. address: $001e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 10-6. pll programming register (ppg) interrupts mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 139 note the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs7?vrs4 ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency, f vrs . (see 10.3.2.1 circuits , 10.3.2.4 programming the pll , and 10.5.1 pll control register .) vrs7?vrs4 cannot be written when the pllon bit in the pll control register (pctl) is set. see 10.3.2.5 special programming exceptions . a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. (see 10.3.3 base clock selector circuit and 10.3.2.5 special programming exceptions for more information.) reset initializes the bits to $6 to give a default range multiply value of 6. note the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. 10.6 interrupts when the auto bit is set in the pll bandwidth c ontrol register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupt requests from the pll. pllf, the interrupt flag in the pctl, becomes set whether cpu interrupt requests are enabled or not. when the auto bit is clear, cpu interrupt requests from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll cpu interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precaution s should be taken. if the application is not frequency sensitive, cpu interrupt requests should be disabled to prevent pll interrupt service routines from impeding software performance or fr om exceeding stack limitations. table 10-3. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco fr equency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 140 freescale semiconductor note software can select the cgmvclk divi ded by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 10.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 10.7.1 wait mode the cgm remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. 10.7.2 stop mode the stop instruction disables the cgm and ho lds low all cgm outputs (cgmxclk, cgmout, and cgmint). if cgmout is being driven by cgmvclk and a stop in struction is executed; the pll will clear the bcs bit in the pll control register, causing cgmout to be driven by cgmxclk. when the mcu recovers from stop, the crystal clock divided by tw o drives cgmout and bcs remains clear. 10.8 cgm during break interrupts the bcfe bit in the break flag control register (bfc r) enables software to clear status bits during the break state. see chapter 13 break module (brk) . to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll cont rol register during the break state without affecting the pllf bit. 10.9 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensure s the highest stability and lowest acquisition/lock times. 10.9.1 acquisition/ lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually sp ecified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to acquisition/lock ti me specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 141 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a ?100 khz noise hit, the acquisition time is the time tak en to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as t he time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition beca use the system requires the output frequency to be within a certain tolerance of the desired frequenc y regardless of the size of the initial error. the discrepancy in these definitions makes it difficul t to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are: ? acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to le ss than the tracking mode entry tolerance, trk . acquisition time is based on an initial frequency error, (f des ?f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 10.3.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). ? lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, lock . lock time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). (see 10.3.2.3 manual and automatic pll bandwidth modes ). obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 10.9.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still pr oviding the highest possible stability. these reaction times are not constant, however . many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reac tion times of the pll is the reference frequency, f cgmrdv (please reference figure 10-1 ). this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f cgmxclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. see 10.9.3 choosing a filter capacitor . also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. va riable supplies, such as batteries, are acceptable if they vary within a known range at very slow sp eeds. noise on the power s upply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 142 freescale semiconductor temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as spec ified as long as thes e influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacito r, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 10.9.3 choosing a filter capacitor as described in 10.9.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. t he pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, theref ore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to this equation: for acceptable values of c fact , (see chapter 28 electrical specifications ). for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly av ailable capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll may become unstable. also, always choose a ca pacitor with a tight tolerance ( 20% or better) and low dissipation. 10.9.4 reaction ti me calculation the actual acquisition and lock times can be calculated using the equations below. these equations yield nominal values under the following conditions: ? correct selection of filter capacitor, c f (see 10.9.3 choosing a filter capacitor ). ? room temperature operation ? negligible external leakage on cgmxfc ? negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. (see 10.3.2.2 acquisition and tracking modes ). note the inverse proportionality between the lock time and the reference frequency. c f c fact v dda f cgmrdv ------------------ - ?? ?? = t acq v dda f cgmrdv ------------------- - ?? ?? 8 k acq ------------ - ?? ?? = t al v dda f cgmrdv ------------------- - ?? ?? 4 k trk ----------- - ?? ?? = t lock t acq t al + = acquisition/lock ti me specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 143 in automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (see 10.3.2.3 manual and automatic pll bandwidth modes ). a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f cgmrdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f cgmrdv . also, since the average frequency over the entire me asurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see 10.3.3 base clock selector circuit ), because the factors described in 10.9.2 parametric influences on reaction time , may slow the lock time considerably. when defining a limit in software for the maximum lock time, the value must allow for variation due to all of the factors mentioned in this chapter, especially due to the c f capacitor and application specific influences. the calculated lock time is only an indication and it is the customer?s responsibility to allow enough of a guard band for their application. prior to finalizing any software and while determining the maximum lock time, take into account all device to device differe nces. typically, applications set the maximum lock time as an order of magnitude higher than the measured value. this is considered sufficient for all such device to device variation. freescale recommends measuring the lo ck time of the application syste m by utilizing dedicated software, running in flash, eeprom or ram. this should to ggle a port pin when the pll is first configured and switched on, then again when it goes from acquisition to lock mode and finally again when the pll lock bit is set. the resultant waveform can be captur ed on an oscilloscope and used to determine the typical lock time for the microcontroller and the associated external application circuit. for example, note the filter capacitor should be fully discharged prior to making any measurements. t lock t acq t al t trk complete and lock set init. low signal on port pin t acq complete pll configured and switched on clock generator module (cgm) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 144 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 145 chapter 11 configuration register (config-1) 11.1 introduction this chapter describes the configuration register (c onfig-1), which contains bits that configure these options: ? resets caused by the lvi module ? power to the lvi module ? lvi enabled during stop mode ? stop mode recovery time (32 cgmx clk cycles or 4096 cgmxclk cycles) ? computer operating properly module (cop) ? stop instruction enable/disable. 11.2 functional description the configuration register is a write-once register. ou t of reset, the configuration register will read the default value. once the register is written, furt her writes will have no effect until a reset occurs. note if the lvi module and the lvi reset si gnal are enabled, a reset occurs when v dd falls to a voltage, lvi tripf , and remains at or below that level for at least nine consecutive cpu cycles. on ce an lvi reset occurs, the mcu remains in reset until v dd rises to a voltage, lvi tripr . lvistop ? lvi stop mode enable bit lvistop enables the lvi module in stop mode. (see chapter 16 low-voltage inhibit (lvi) ). 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode note to have the lvi enabled in stop mode, the lvipwr must be at a logic 1 and the lvistop bit must be at a logic 1. take note that by enabling the lvi in stop mode, the stop i dd current will be higher. address: $001f bit 7654321bit 0 read: lvistop r lvirst lvipwr ssrec copl stop copd write: reset:01110000 r=reserved figure 11-1. configuration register (config-1) configuration register (config-1) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 146 freescale semiconductor lvirst ? lvi reset enable bit lvirst enables the reset signal from the lvi module. (see chapter 16 low-voltage inhibit (lvi) ). 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr enables the lvi module. (see chapter 16 low-voltage inhibit (lvi) ). 1 = lvi module power enabled 0 = lvi module power disabled ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. (see 9.6.2 stop mode ). 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note if using an external crystal oscillator, do not set the ssrec bit. copl ? cop long timeout copl enables the shorter cop timeout period. (see chapter 15 computer operating properly (cop) ). 1 = cop timeout period is 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period is 2 18 ? 2 4 cgmxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. (see chapter 15 computer operating properly (cop) ). 1 = cop module disabled 0 = cop module enabled warning extra care should be exercised when using this emulation part for development of code to be run in rom az, ab or as parts that the options selected by setting the config-1 register match exactly the options selected on any rom code request submitted. the enable/disable logic is not necessarily identical in all parts of the as and az families. if in doubt, check with your local field applications representative. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 147 chapter 12 configuration register (config-2) 12.1 introduction this chapter describes the configuration register (con fig-2). this register cont ains bits that configure these options: ? configures the device to either the mc68hc 08azxx emulator or the mc68hc08asxx emulator ? disables the can module 12.2 functional description the configuration register is a write-once register. ou t of reset, the configuration register will read the default. once the register is written, further writes will have no effect until a reset occurs. at60a ? device indicator this read-only bit is used to distinguish an mc68hc908as60a and mc68hc908az60a from older non-?a? suffix versions. 1 = ?a? version 0 = non-?a? version eedivclk ? eeprom timebase di vider clock select bit this bit selects the reference clock source for the eeprom-1 and eeprom -2 timebase divider modules. 1 = eexdiv clock input is driven by internal bus clock 0 = eexdiv clock input is driven by cgmxclk mscand ? mscan disable bit mscand disables the mscan module. (see chapter 23 mscan controller (mscan08) ). 1 = mscan module disabled 0 = mscan module enabled address: $fe09 bit 7654321bit 0 read: eediv clk rrmscand at60a rrazxx write: r reset:00011000 r = reserved figure 12-1. configuration register (config-2) configuration register (config-2) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 148 freescale semiconductor azxx ? azxx emulator enable bit azxx enables the mc68hc08azxx emulator config uration. this bit will be 0 out of reset. 1 = mc68hc08azxx emulator enabled 0 = mc68hc08asxx emulator enabled note azxx bit is reset by a power-on-reset only. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 149 chapter 13 break module (brk) 13.1 introduction the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 13.2 features ? accessible i/o register s during break interrupts ? cpu-generated break interrupts ? software-generated break interrupts ? cop disabling during break interrupts 13.3 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu th en loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: ? a cpu-generated address (the address in the program counter) matches the contents of the break address registers. ? software writes a 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 13-1 shows the structure of the break module. break module (brk) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 150 freescale semiconductor figure 13-1. break module block diagram register name bit 7654321bit 0 break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 break status and control register (bscr) read: brke brka 000000 write: reset:00000000 = unimplemented figure 13-2. i/o register summary table 13-1. i/o register address summary register brkh brkl bscr address $fe0c $fe0d $fe0e iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] break low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 151 13.3.1 flag protectio n during break interrupts the bcfe bit in the break flag control register (bfc r) enables software to clear status bits during the break state. 13.3.2 cpu during break interrupts the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. 13.3.3 tim during break interrupts a break interrupt stops the timer counter. 13.3.4 cop during break interrupts the cop is disabled during a break interrupt when v hi is present on the rst pin. 13.4 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 13.4.1 wait mode if enabled, the break module is active in wait mode. the sim break wait bit (bw) in the sim break status register indicates whether wait was exited by a break interrupt. if so, the user can modify the return address on the stack by subtracting one from it. (see 9.7.1 sim break status register ). 13.4.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 13.5 break module registers these registers control and monitor operation of the break module: ? break address register high (brkh) ? break address register low (brkl) ? break status and control register (bscr) break module (brk) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 152 freescale semiconductor 13.5.1 break status and control register the break status and control register cont ains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match 13.5.2 break addr ess registers the break address registers contain the high and lo w bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 13-3. break status and control register (bscr) register: brkh brkl address: $fe0c $fe0d bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 read: bit 7654321bit 0 write: reset:00000000 figure 13-4. break address registers (brkh and brkl) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 153 chapter 14 monitor rom (mon) 14.1 introduction this chapter describes the monitor rom (mon). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. 14.2 features features of the monitor rom include: ? normal user-mode pin functionality ? one pin dedicated to serial communication between monitor rom and host computer ? standard mark/space non-return-to-zero (nrz) communication with host computer ? up to 28.8 kbaud communication with host computer ? execution of code in ram or flash ? flash security ? flash programming 14.3 functional description monitor rom receives and executes commands from a host computer. figure 14-1 shows a sample circuit used to enter monitor mode and communic ate with a host computer via a standard rs-232 interface. while simple monitor commands can access any memory address, the mc68hc908as60a and mc68hc908az60a have a flash security feature to pr event external viewing of the contents of flash. proper procedures must be followed to verify fl ash content. access to the flash is denied to unauthorized users of customer specified software (see 14.3.8 security ). in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins except pta0 retain normal operating mode functions. all comm unication between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexi ng interface is required between pta0 and the host computer. pta0 is used in a wired-or c onfiguration and requires a pullup resistor. monitor rom (mon) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 154 freescale semiconductor figure 14-1. monitor mode circuit + + + 10 m x1 v dd v hi mc145407 mc74hc125 68hc08 rst irq cgmxfc osc1 osc2 v ss v dd pta0 v dd 10 k 0.1 f 0.022 f 1 k 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ptc3 v dd 10 k b a note: position a ? bus clock = cgmxclk 4 or cgmvclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 + ptc0 ptc1 v dd 10 k v ssa * * = refer to table 14-9 and table 14-10 for correct value. 9.1v 0.1 f v dda /v ddaref v dda v dd functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 155 14.3.1 entering monitor mode table 14-1 shows the pin conditions for entering monitor mode. enter monitor mode by either ? executing a software interrupt instruction (swi) or ? applying a logic 0 and then a logic 1 to the rst pin. once out of reset, the mcu waits for the host to send eight security bytes (see 14.3.8 security ). after the security bytes, the mcu sends a break signal (10 co nsecutive logic 0s) to t he host computer, indicating that it is ready to receive a command. monitor mode uses alternate vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v hi (see 28.1.4 5.0 volt dc electrical characteristics ), is applied to either the irq pin or the reset pin. (see chapter 9 system integration module (sim) for more information on modes of operation). note holding the ptc3 pin low when enter ing monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 14-2 is a summary of the differences between user mode and monitor mode. table 14-1. mode selection irq pin ptc0 pin ptc1 pin pta0 pin ptc3 pin mode cgmout bus frequency v hi (1) 1011 monitor or v hi (1) 1 0 1 0 monitor cgmxclk 1. for v hi , 28.1.4 5.0 volt dc electrical characteristics , and 28.1.1 maximum ratings . table 14-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v hi ) is removed from the irq and/or reset pin while in monitor mode, the sim asserts its cop enable output. the cop is enabled or disabled by the copd bit in the configuration register. (see 28.1.4 5.0 volt dc electr ical characteristics ). $fefe $feff $fefc $fefd $fefc $fefd cgmxclk 2 ----------------------------- cgmvclk 2 ----------------------------- cgmout 2 -------------------------- cgmout 2 -------------------------- monitor rom (mon) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 156 freescale semiconductor 14.3.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. (see figure 14-2 and figure 14-3 .) the data transmit and receive rate can be anywhere up to 28.8 kbaud. transmit and receive baud rates must be identical. figure 14-2. monitor data format figure 14-3. sample monitor waveforms 14.3.3 echoing as shown in figure 14-4 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. any result of a command appears after the echo of the last byte of the command. figure 14-4. read transaction 14.3.4 break signal a start bit followed by nine low bits is a break signal. (see figure 14-5 ). when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits before echoing the break signal. figure 14-5. break transaction bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 157 14.3.5 commands the monitor rom uses these commands: ? read, read memory ? write, write memory ? iread, indexed read ? iwrite, indexed write ? readsp, read stack pointer ? run, run user program a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 14-3. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence table 14-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result addr. high write write addr. high addr. low addr. low data echo sent to monitor data monitor rom (mon) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 158 freescale semiconductor table 14-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 14-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence table 14-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointe r in high byte:low byte order opcode $0c command sequence data iread iread data echo sent to monitor result data iwrite iwrite data echo sent to monitor sp high readsp readsp sp low echo sent to monitor result functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 159 14.3.6 mc68hc908as60a baud rate with a 4.9152-mhz crystal and the ptc3 pin at lo gic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, t he baud rate is determined by the mul[7:4] bits in the pll programming register (ppg). (see chapter 10 clock generator module (cgm) ). table 14-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence table 14-9. mc68hc908as60a monitor baud rate selection monitor baud rate vco frequency multiplier (n) 123456 4.9152 mhz 4800 9600 14,400 19,200 24,000 28,800 4.194 mhz 4096 8192 12,288 16,384 20,480 24,576 run run echo sent to monitor monitor rom (mon) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 160 freescale semiconductor 14.3.7 mc68hc908az60a baud rate the mc68hc908az60a features a monitor mode which is optimised to operate with either a 4.9152 mhz crystal clock source (or multiples of 4.9152 mhz) or a 4 mhz crystal (or multiple s of 4 mhz). this supports designs which use the mscan module, which is generally clocked from a 4 mhz, 8 mhz or 16 mhz internal reference clock. the table below outlines the available baud rate s for a range of crystals and how they can match to a pc baud rate. warning care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure. 14.3.8 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. if flash is unprogrammed, the eight security byte values to be sent are $ff, the unprogrammed state of flash. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pa0. table 14-10 mc68hc908az60a monitor baud rate selection baud rate closest pc baud pc error % clock freq ptc3=0 ptc3=1 ptc3=0 ptc3=1 ptc3=0 ptc3=1 32khz 57.97 28.98 57.6 28.8 0.64 0.63 1mhz 1811.59 905.80 1800 900 0.64 0.64 2mhz 3623.19 1811.59 3600 1800 0.64 0.64 4mhz 7246.37 3623.19 7200 3600 0.64 0.64 4.194mhz 7597.83 3798.91 7680 3840 1.08 1.08 4.9152mhz 8904.35 4452.17 8861 4430 0.49 0.50 8mhz 14492.72 7246.37 14400 7200 0.64 0.64 16mhz 28985.51 14492.75 28800 14400 0.64 0.64 functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 161 figure 14-6. monitor mode entry timing if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. after the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. if the reset was not a power-on reset, the security remains bypassed regardless of the data that the host sends. if the received bytes do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading flash locations returns undefined data, and trying to execute code from flas h causes an illegal address reset. after the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. after receiving the eight security bytes from the hos t, the mcu transmits a break character signalling that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 24 bus cycles (minimum) 1 4 1 1 2 1 break note: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 4 = wait 1 bit time before sending next byte. 4 from host from mcu monitor rom (mon) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 162 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 163 chapter 15 computer operating properly (cop) 15.1 introduction the cop module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prev ent a cop reset by periodically clearing the cop counter. 15.2 functional description the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 13 ?2 4 or 2 18 ?2 4 cgmxclk cycles, depending on the state of the cop long timeout bit, copl, in the config-1. when copl = 0, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by cl earing the cop counter and stages 4?12 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq pin is held at v hi . during the break state, v hi on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 15.3 i/o signals the following paragraphs describe the signals shown in figure 15-1 . computer operating properly (cop) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 164 freescale semiconductor figure 15-1. cop block diagram 15.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cg mxclk frequency is equal to the crystal frequency. 15.3.2 stop instruction the stop instruction clears the cop prescaler. 15.3.3 copctl write writing any value to the cop control register (copctl) (see 15.4 cop control register ), clears the cop counter and clears stages 12 through 4 of the cop prescaler. reading the cop control register returns the reset vector. 15.3.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 15.3.5 internal reset an internal reset clears the cop prescaler and the cop counter. copctl write cgmxclk reset vector fetch reset reset status internal reset sources stop instruction clear stages 4?12 clear all stages 6-bit cop counter copd from config-1 reset copctl write clear cop counter copl from config-1 12-bit cop prescaler register cop control register mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 165 15.3.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 15.3.7 copd the copd signal reflects the state of the cop dis able bit (copd) in the configuration register. (see chapter 11 configuration register (config-1) ). 15.3.8 copl the copl signal reflects the state of the cop rate se lect bit. (copl) in the configuration register. (see chapter 11 configuration register (config-1) ). 15.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 15.5 interrupts the cop does not generate cpu interrupt requests. 15.6 monitor mode the cop is disabled in monitor mode when v hi is present on the irq pin or on the rst pin. 15.7 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 15.7.1 wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 15-2. cop control register (copctl) computer operating properly (cop) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 166 freescale semiconductor 15.7.2 stop mode stop mode turns off the cgmxclk input to the co p and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the configuration register (con fig) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instru ction, disable the stop instruction by clearing the stop bit. 15.8 cop module du ring break interrupts the cop is disabled during a break interrupt when v hi is present on the rst pin. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 167 chapter 16 low-voltage inhibit (lvi) 16.1 introduction this chapter describes the low-voltage inhibit modul e (lvi47, version a), which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 16.2 features features of the lvi module include: ? programmable lvi reset ? programmable power consumption ? digital filtering of v dd pin level note if a low voltage interrupt (lvi) occurs during programming of eeprom or flash memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. it is the responsibility of the user to ensure that in the event of an lvi any addresses being programmed receive specific ation programming conditions. 16.3 functional description figure 16-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for nine or more consecutive cpu cycles. note that short v dd spikes may not trip the lvi. it is the user?s responsibility to ensure a clean v dd signal within the specified operating voltage range if no rmal microcontroller oper ation is to be guaranteed. lvistop, enables the lvi module during stop mode. this will ensure when the stop instruction is implemented, the lvi will continue to monitor the voltage level on v dd . lvipwr, lvistop, and lvirst are in the configuration register, config-1 (see chapter 11 configuration register (config-1) ). once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr . v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset (see 16.3.2 forced reset operation ). the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. low-voltage inhibit (lvi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 168 freescale semiconductor figure 16-1. lvi module block diagram 16.3.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bit. in the confi guration register, the lvipwr bit must be at logic 1 to enable the lvi module, and the lvirst bit must be at logic 0 to disable lvi resets. 16.3.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the lvi tripf level and remains at or below that level for nine or more consecutive cpu cycles. in the configuration register, the lvip wr and lvirst bits must be at logic 1 to enable the lvi module and to enable lvi resets. 16.3.3 false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lvi module to reset the mcu,v dd must remain at or below the lvi tripf level for nine or more consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. addr. register name bit 7654321bit 0 $fe0f lvi status register (lvisr) read:lviout0000000 write: = unimplemented figure 16-2. lvi i/o register summary low v dd lvirst v dd > lvi trip = 0 v dd < lvi trip = 1 lviout lvipwr detector v dd lvi reset from config-1 from config-1 v dd digital filter cpu clock anlgtrip stop mode filter bypass lvistop from config-1 lvi status register mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 169 16.4 lvi status register the lvi status register flags v dd voltages below the lvi tripf level . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the lvi tripf voltage for 32 to 40 cgmxclk cycles. (see table 16-1 ). reset clears the lviout bit. 16.5 lvi interrupts the lvi module does not generate interrupt requests. 16.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.6.1 wait mode with the lvipwr bit in the configur ation register programmed to 1, the lvi module is active after a wait instruction. with the lvirst bit in the confi guration register programmed to 1, the lvi module can generate a reset and bring the mcu out of wait mode. address: $fe0f bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 16-3. lvi status register (lvisr) table 16-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > lvi tripr any 0 v dd < lv i tripf < 32 cgmxclk cycles 0 v dd < lv i tripf between 32 and 40 cgmxclk cycles 0 or 1 v dd < lv i tripf > 40 cgmxclk cycles 1 lv i tripf < v dd < lv i tripr any previous value low-voltage inhibit (lvi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 170 freescale semiconductor 16.6.2 stop mode with the lvistop and lvipwr bits in the configuration register programmed to a logic 1, the lvi module will be active after a stop instruction. because cpu clocks are disabled during stop mode, the lvi trip must bypass the digital filter to generate a reset and bring the mcu out of stop. with the lvipwr bit in the configuration register pr ogrammed to logic 1 and the lvistop bit at a logic 0, the lvi module will be inactive after a stop instruction. note the lvi feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application v dd voltage collapsing completely to an unsafe level. it is not intended that users operate the microcontroller at lower than specified operating voltage v dd . mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 171 chapter 17 external interrupt module (irq) 17.1 introduction this chapter describes the nonmaskabl e external interrupt (irq) input. 17.2 features features include: ? dedicated external interrupt pin (irq ) ? hysteresis buffer ? programmable edge-only or edge- and level-interrupt sensitivity ? automatic interrupt acknowledge 17.3 functional description a falling edge applied to the external interrupt pin can latch a cpu interrupt request. figure 17-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: ? vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. ? software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack bit clears the irq latch. ? reset ? a reset automatically clears both interrupt latches. external interrupt module (irq) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 172 freescale semiconductor figure 17-1. irq block diagram the external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. the mode bit in the iscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interr upt latch remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: ? vector fetch or software clear ? return of the interrupt pin to a high level the vector fetch or software clear may occur before or after the interrupt pin returns to a high level. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode1 control bit, thereby clearing the in terrupt even if the pin stays low. when set, the imask bit in the iscr masks all exter nal interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the co rresponding imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. (see figure 17-3 ). addr. register name bit 7654321bit 0 $001a irq status/control register (iscr) read:0000irqf0 imask mode write:rrrrrack r = reserved figure 17-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 173 figure 17-3. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction. swi instruction? rti instruction? no stack cpu registers. no set i bit. load pc with interrupt vector. no yes unstack cpu registers. execute instruction. yes yes external interrupt module (irq) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 174 freescale semiconductor 17.4 irq pin a falling edge on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge sensitive and low-level sensitive. with mode set, both of the following actions mu st occur to clear the irq latch: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (iscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latc h. writing to the ack bit can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge on irq that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu load s the program counter with the vector address at locations $fffa and $fffb. ? return of the irq pin to a high level ? as long as the irq pin is low, the irq1 latch remains set. the vector fetch or software clear and the return of the irq pin to a high level can occur in any order. the interrupt request remains pending as long as the irq pin is low. a reset will clear the latch and the mode control bit, thereby clearing the in terrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the iscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 17.5 irq module du ring break interrupts the system integration module (sim) controls whether the irq interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latches during the break state. (see 9.7.3 sim break flag control register .) to allow software to clear the irq latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. irq status and control register mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 175 17.6 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has these functions: ? shows the state of the irq interrupt flag ? clears the irq interrupt latch ? masks irq interrupt request ? controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001a bit 7654321bit 0 read:0000irqf0 imask mode write:rrrr ack reset:00000000 = unimplemented r = reserved figure 17-4. irq status and control register (iscr) external interrupt module (irq) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 176 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 177 chapter 18 serial communications interface (sci) 18.1 introduction the sci allows asynchronous communications with peripheral devices and other mcus. 18.2 features the sci module?s features include: ? full duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 32 programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? separate receiver and transmitter cpu interrupt requests ? programmable transmitter output polarity ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? interrupt-driven operation with eight interrupt flags: ? transmitter empty ?transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection 18.3 pin name conventions the generic names of the sci input/output (i/o) pins are: ? rxd (receive data) ? txd (transmit data) sci i/o lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 18-1 shows the full names and the generic names of the sci i/o pins.the generic pin names appear in the text of this subsection. serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 178 freescale semiconductor 18.4 functional description figure 18-1 shows the structure of the sci module. the sc i allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices , including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 18-1. sci module block diagram table 18-1. pin name conventions generic pin names rxd txd full pin names pte1/scrxd pte0/sctxd scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator cgmxclk rxd txd functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 179 register name bit 7654321bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset:uu000000 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 sci status register 2 (scs2) read:000000bkfrpf write: reset:00000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented u = unaffected r = reserved figure 18-2. sci i/o register summary table 18-2. sci i/o register address summary register scc1 scc2 scc3 scs1 scs2 scdr scbr address $0013 $0014 $0015 $0016 $0017 $0018 $0019 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 180 freescale semiconductor 18.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 18-3 . figure 18-3. sci data formats 18.4.2 transmitter figure 18-4 shows the structure of the sci transmitter. 18.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9- bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 18.4.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the tr ansmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit (scte) by fi rst reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into t he least significant bit position of the transmit shift register. a 1 stop bit goes into t he most significant bit position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, 1. if at any time software clears the ensci bit in sci c ontrol register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 181 figure 18-4. sci transmitter register name bit 7654321bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected r = reserved figure 18-5. sci transmitter i/o register summary pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc cgmxclk parity generation msb sci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte transmitter cpu int errupt request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 txd serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 182 freescale semiconductor 18.4.2.3 break characters writing a logic 1 to the send break bit, sbk, in s cc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, tran smitter logic cont inuously loads break characters into the transmit shift register. afte r software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or ni ne logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has the following effects on sci registers: ? sets the framing error bit (fe) in scs1 ? sets the sci receiver full bit (scrf) in scs1 ? clears the sci data register (scdr) ? clears the r8 bit in scc3 ? sets the break flag bit (bkf) in scs2 ? may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 table 18-3. sci transmitter i/o address summary register scc1 scc2 scc3 scs1 scdr scbr address $0013 $0014 $0015 $0016 $0018 $0019 register name bit 7654321bit 0 = unimplemented u = unaffected r = reserved figure 18-5. sci transmitter i/o register summary (continued) functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 183 18.4.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when a break sequence is followed immedi ately by an idle character, this sci design exhibits a condition in wh ich the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or ni ne data bits (as defined by the m bit in scc1) of logic 0 and one half data bit length of logic 0 in the stop bit position followed immediately by the idle char acter. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 18.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 18.8.1 sci control register 1 .) 18.4.2.6 transmitter interrupts the following conditions can generate cpu in terrupt requests from the sci transmitter: ? sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. ? transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 18.4.3 receiver figure 18-6 shows the structure of the sci receiver. serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 184 freescale semiconductor figure 18-6. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 cgmxclk rxd functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 185 register name bit 7654321bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset:uu000000 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 sci status register 2 (scs2) read:000000bkfrpf write: reset:00000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented u = unaffected r = reserved figure 18-7. sci i/o receiver register summary table 18-4. sci receiver i/o address summary register scc1 scc2 scc3 scs1 scs2 scdr scbr address $0013 $0014 $0015 $0016 $0017 $0018 $0019 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 186 freescale semiconductor 18.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 18.4.3.2 character reception during an sci reception, the receive shift register shi fts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 18.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 18-8 ): ? after every start bit ? after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an a synchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 18-8. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 187 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 18-5 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 18-6 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. table 18-5. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 18-6. data bit recovery rt8, rt9, and rt10 samples dat a bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 188 freescale semiconductor to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 18-7 summarizes the results of the stop bit samples. 18.4.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break ch aracter also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. 18.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 18-9 shows how much a slow received characte r can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 18-9. slow data table 18-7. stop bit recovery rt8, rt9, and rt10 samples f raming error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 189 for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 18-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 18-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 18-10 shows how much a fast received character can be misaligned wit hout causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 18-10. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 18-10 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 18-10 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. 154 147 ? 154 ------------- ------------ - 100 4.54% = 170 163 ? 170 ------------- ------------ - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------ ------------- - 100 3.90%. = serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 190 freescale semiconductor the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 18.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: ? address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address ma rk wakes the receiver from the standby state by clearing the rwu bit. the address mark also se ts the sci receiver full bit, scrf. software can then compare the character containing the addr ess mark to the user-defined address of the receiver. if they are the same, the receiver re mains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. ? idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 18.4.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: ? sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. ? idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 18.4.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: ? receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. 170 176 ? 170 ------------ ------------- - 100 3.53%. = low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 191 ? noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. ? framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. ? parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. 18.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 18.5.1 wait mode the sci module remains active in wait mode. an y enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 18.5.2 stop mode the sci module is inactive in stop mode. the stop in struction does not affect sci register states. any enabled cpu interrupt request from the sci module does not bring the mcu out of stop mode. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 18.6 sci during br eak module interrupts the bcfe bit in the break flag control register (bfc r) enables software to clear status bits during the break state. (see chapter 13 break module (brk) ). to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a two-step read/write clearin g procedure. if software does the first step on such a bit before the break, the bit cannot change during the brea k state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 192 freescale semiconductor 18.7 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: ? pte0/sctxd ? transmit data ? pte1/scrxd ? receive data 18.7.1 pte0/sctxd (transmit data) the pte0/sctxd pin is the serial data output from the sci transmitter. the sci shares the pte0/sctxd pin with port e. when the sci is enabled, the pte0/sctxd pin is an output regardless of the state of the ddre2 bit in data direction register e (ddre). 18.7.2 pte1/scrxd (receive data) the pte1/scrxd pin is the serial data input to t he sci receiver. the sci shares the pte1/scrxd pin with port e. when the sci is enabled, the pte1/scrxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 18.8 i/o registers the following i/o registers control and monitor sci operation: ? sci control register 1 (scc1) ? sci control register 2 (scc2) ? sci control register 3 (scc3) ? sci status register 1 (scs1) ? sci status register 2 (scs2) ? sci data register (scdr) ? sci baud rate register (scbr) 18.8.1 sci cont rol register 1 sci control register 1: ? enables loop mode operation ? enables the sci ? controls output polarity ? controls character length ? controls sci wakeup method ? controls idle character detection ? enables parity function ? controls parity type i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 193 loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit inverts all tran smitted values, including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether sci c haracters are eight or nine bits long. (see table 18-8 ).the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts coun ting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but require s properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake illty pen pty write: reset:00000000 figure 18-11. sci control register 1 (scc1) serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 194 freescale semiconductor 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. (see table 18-8 ). when enabled, the parity function inserts a parity bit in the most significant bit position. (see table 18-7 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci gen erates and checks for odd parity or even parity. (see table 18-8 ). reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. 18.8.2 sci cont rol register 2 sci control register 2: ? enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests ? enables the transmitter ? enables the receiver ? enables sci wakeup ? transmits sci break characters table 18-8. character format selection control bits character format m pen:pty start bits data bits parity stop bits character length 00x 18none1 10 bits 10x 19none1 11 bits 010 17even1 10 bits 011 17odd1 10 bits 110 18even1 11 bits 111 18odd1 11 bits i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 195 sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to gener ate sci transmitter cpu interrupt requests. setting the sctie bit in scc3 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generat e cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 18-12. sci control register 2 (scc2) serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 196 freescale semiconductor re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously tr ansmits break characters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 18.8.3 sci cont rol register 3 sci control register 3: ? stores the ninth sci data bit received and the ninth sci data bit to be transmitted. ? enables the following interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented r = reserved u = unaffected figure 18-13. sci control register 3 (scc3) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 197 r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a co py of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. rese t has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 18.8.4 sci status register 1 sci status register 1 contains flags to signal the following conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error ? parity error serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 198 freescale semiconductor scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt reques t. in normal operation, clear the scte bit by reading scs1 with scte set and then wr iting to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an sci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 18-14. sci status register 1 (scs1) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 199 or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 18-15 shows the normal flag-clearing sequenc e and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. figure 18-15. flag clearing sequence nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an sci error cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 200 freescale semiconductor fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a sci receiver cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 18.8.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: ? break character detected ? incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again on ly after 1s appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the sci module or ente ring stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 18-16. sci status register 2 (scs2) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 201 18.8.6 sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $0018 accesses the read-only rece ived data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. note do not use read-modify-write instructions on the sci data register. 18.8.7 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 18-9 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 18-10 . reset clears scr2?scr0. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 18-17. sci data register (scdr) address: $0019 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 18-18. sci baud rate register (scbr) table 18-9. sci baud rate prescaling scp[1:0] prescaler divisor (pd) 00 1 01 3 10 4 11 13 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 202 freescale semiconductor use the following formula to calculate the sci baud rate: where: f crystal = crystal frequency pd = prescaler divisor bd = baud rate divisor table 18-11 shows the sci baud rates that can be generated with a 4.9152-mhz crystal. table 18-10. sci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f crystal 64 pd bd ------------------------------------ = i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 203 table 18-11. sci baud rate selection examples scp[1:0] prescaler divisor (pd) scr[2:1:0] baud rate divisor (bd) baud rate (f crystal = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 serial communications interface (sci) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 204 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 205 chapter 19 serial peripheral interface (spi) 19.1 introduction this chapter describes the serial peripheral in terface (spi) module, wh ich allows full-duplex, synchronous, serial communicati ons with peripheral devices. 19.2 features features of the spi module include: ? full-duplex operation ? master and slave modes ? double-buffered operation with se parate transmit and receive registers ? four master mode frequencies (maximum = bus frequency 2) ? maximum slave mode frequency = bus frequency ? serial clock with programmable polarity and phase ? two separately enabled interrupts with cpu service: ? sprf (spi receiver full) ? spte (spi transmitter empty) ? mode fault error flag with cpu interrupt capability ? overflow error flag with cpu interrupt capability ? programmable wired-or mode ?i 2 c (inter-integrated circuit) compatibility 19.3 pin name and regi ster name conventions the generic names of the spi input/output (i/o) pins are: ?ss (slave select) ? spsck (spi serial clock) ? mosi (master out slave in) ? miso (master in slave out) the spi shares four i/o pins with a parallel i/o port. the full name of an spi pin reflects the name of the shared port pin. table 19-1 shows the full names of the spi i/o pins. the generic pin names appear in the text that follows. table 19-1. pin name conventions spi generic pin name miso mosi ss spsck full spi pin name pte5/miso pte6/mosi pte4/ss pte7/spsck serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 206 freescale semiconductor the generic names of the spi i/o registers are: ? spi control register (spcr) ? spi status and control register (spscr) ? spi data register (spdr) table 19-2 shows the names and the addresses of the spi i/o registers. 19.4 functional description figure 19-1 summarizes the spi i/o registers and figure 19-2 shows the structure of the spi module. the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. all spi interrupts can be serviced by the cpu. the following paragraphs describe the operation of the spi module. table 19-2. i/o register addresses register name address spi control register (spcr) $0010 spi status and control register (spscr) $0011 spi data register (spdr) $0012 addrregister namer/wbit 7654321bit 0 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r = reserved = unimplemented figure 19-1. spi i/o register summary functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 207 figure 19-2. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus bus clock modfen errie control modf spmstr mosi miso spsck ss serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 208 freescale semiconductor 19.4.1 master mode the spi operates in master mode when the spi master bit, spmstr (spcr $0010), is set. note configure the spi modules as mast er and slave before enabling them. enable the master spi before enabling t he slave spi. disable the slave spi before disabling the master spi. see 19.13.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte (spscr $0011). the byte begins shifting out on the mosi pin under the control of the serial clock. (see table 19-3 ). the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 19.13.2 spi status and control register ). through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. figure 19-3. full-duplex master-slave connections as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends wh en the receiver full bit, sprf (spscr), becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears spr f by reading the spi status and control register and then reading the spi data register. writing to the spi data register clears the sptie bit. 19.4.2 slave mode the spi operates in slave mode when the spmstr bit (spcr, $0010) is clear. in slave mode the spsck pin is the input for the serial cl ock from the master mcu. before a data transmission occurs, the ss pin of the slave mcu must be low. ss must remain low until the transmission is complete. (see 19.6.2 mode fault error ). in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it is transferred to the receive data register, and the sprf bit (spscr) is set. to prev ent an overflow condition, slave software then must read the spi data register before another byte enters the shift register. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss transmission formats mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 209 the maximum frequency of the spsck for an spi confi gured as a slave is the bus clock speed, which is twice as fast as the fastest master spsck clock that can be generated. the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 19.5 transmission formats . if the write to the data register is late, the spi transm its the data already in the shift register from the previous transmission. note to prevent spsck from appearing as a clock edge, spsck must be in the proper idle state before the slave is enabled. 19.5 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock line synchronizes shifti ng and sampling on the two serial data lines. a slave select line allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi dev ice, the slave select line can be used optionally to indicate a multiple-master bus contention. 19.5.1 clock phase and polarity controls software can select any of four combinations of seri al clock (sck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signifi cant effect on the transmission format. the clock phase (cpha) control bit (spcr) select s one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the pha se and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note before writing to the cpol bit or the cpha bit (spcr), disable the spi by clearing the spi enable bit (spe). serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 210 freescale semiconductor 19.5.2 transmission format when cpha = 0 figure 19-4 shows an spi transmission in which cpha (sp cr) is logic 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfi gured as general-purpose i/o not affecting the spi (see 19.6.2 mode fault error ). when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before th e first spsck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low again between each byte transmitted. figure 19-4. transmission format (cpha = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol = 1 mosi from master miso from slave ss to slave capture strobe transmission formats mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 211 19.5.3 transmission format when cpha = 1 figure 19-5 shows an spi transmission in which cpha (sp cr) is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 19.6.2 mode fault error ). when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 19-5. transmission format (cpha = 1) 19.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), transmissions are started by a software write to the spdr ($0012). cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sck signal. when cpha = 0, the sck si gnal remains inactive for the first half of the first sck cycle. when cpha = 1, the first sck cycle begins with an edge on the sck line from its inactive to its active level. the spi clock rate (selected by spr1?spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 19-6 ). the internal spi clock in the master is a free-running derivative of the inter nal mcu clock. it is only enabled when both the spe and spmstr bits (spcr) are set to conserve power. sck edges occur half way through the low time of the internal mcu clock. since the spi clock is free-running, it is unce rtain where the write to the spdr will occur relative to the slower sck. this uncertainty causes t he variation in the initiation delay shown in figure 19-6 . this bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 1234 5678 sck cycle # for reference sck cpol = 0 sck cpol =1 mosi from master miso from slave ss to slave capture strobe serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 212 freescale semiconductor delay will be no longer than a single spi bit time. that is, the maximum delay between the write to spdr and the start of the spi transmission is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. figure 19-6. transmission start delay (master) write to spdr initiation delay bus mosi sck cpha = 1 sck cpha = 0 sck cycle number msb bit 6 12 clock write to spdr earliest latest sck = internal clock 2; earliest latest 2 possible start points sck = internal clock 8; 8 possible start points earliest latest sck = internal clock 32; 32 possible start points earliest latest sck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? ? ? initiation delay from write spdr to transfer begin error conditions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 213 19.6 error conditions two flags signal spi error conditions: 1. overflow (ovrf in spscr) ? faili ng to read the spi data register bef ore the next byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the spi data register. ovrf is in the spi status and control register. 2. mode fault error (modf in spscr) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. mo df is in the spi status and control register. 19.6.1 overflow error the overflow flag (ovrf in spscr) becomes set if t he spi receive data register still has unread data from a previous transmission when the capture stro be of bit 1 of the next transmission occurs. (see figure 19-4 and figure 19-5 .) if an overflow occurs, the data being rece ived is not transferred to the receive data register so that the unread data can still be read. t herefore, an overflow error always indicates the loss of data. ovrf generates a receiver/error cp u interrupt request if the error in terrupt enable bit (errie in spscr) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 19-9 ). it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if an end-of-block transmission interrupt was meant to pull the mcu out of wait, having an overflow condition without overflow interr upts enabled causes the mcu to hang in wait mode. if the ovrf is enabled to generate an interrupt, it can pull the mcu out of wait mode instead. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 19-7 shows how it is possi ble to miss an overflow. figure 19-7. missed read of overflow condition read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscrw with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is set. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 214 freescale semiconductor the first part of figure 19-7 shows how to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf flag can be set in between the time that spscr and spdr are read. in this case, an overflow can be easily missed. since no more sprf interrupts can be generated until this ovrf is serviced, it will not be obvious that bytes ar e being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr after the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions will comple te with an sprf interrupt. figure 19-8 illustrates this pr ocess. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit (spscr). figure 19-8. clearing sprf when ovrf interrupt is not enabled 19.6.2 mode fault error for the modf flag (in spscr) to be set, the mode fault error enable bit (modfen in spscr) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie in spscr) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 19-9 ). it is not possible to enable only modf or ovrf to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read spdr read spscr ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. error conditions mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 215 in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes low. a mode fault in a master spi causes the following events to occur: ? if errie = 1, the spi generates an spi receiver/error cpu interrupt request. ? the spe bit is cleared. ? the spte bit is set. ? the spi state counter is cleared. ? the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all data direction register (ddr ) bits associated with the spi shared port pins. note setting the modf flag (spscr) does not clear the spmstr bit. reading spmstr when modf = 1 will indicate a mode fault error occurred in either master mode or slave mode. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once t he incoming spsck returns to its idle level after the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level after the shift of the last data bit. (see 19.5 transmission formats ). note when cpha = 0, a modf occurs if a slave is selected (ss is low) and later deselected (ss is high) even if no spsck is sent to that slave. this happens because ss at 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later deselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bi t or reset the spi in any way. software can abort the spi transmission by toggling the spe bit of the slave. note a high voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if a transmission has begun. to clear the modf flag, read the spscr and then wr ite to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag will not be cleared. serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 216 freescale semiconductor 19.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests: the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests. the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt, provided that the spi is enabled (spe = 1). the error interrupt enable bit (errie) enables both the modf and ovrf flags to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf flag is enabled to generate receiver/error cpu interrupt requests. figure 19-9. spi interrupt request generation two sources in the spi status and control register can generate cpu interrupt requests: 1. spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate an spi receiver/error cpu interrupt request. 2. spi transmitter empty (spte) ? the spte bit becom es set every time a by te transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate an spte cpu interrupt request. table 19-3. spi interrupts flag request spte (transmitter empty) spi transmit ter cpu interrupt request (sptie = 1) sprf (receiver full) spi receiver cpu interrupt request (sprie = 1) ovrf (overflow) spi receiver/error interrupt request (sprie = 1, errie = 1) modf (mode fault) spi receiver/error interrupt request (sprie = 1, errie = 1, modfen = 1) spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request queuing transm ission data mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 217 19.8 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag ( spte in spscr) indicates when the transmit data buffer is ready to accept new data. write to the spi data register only when the spte bit is high. figure 19-10 shows the timing associated wi th doing back-to-back transmissi ons with the spi (spsck has cpha:cpol = 1:0). figure 19-10. sprf/spte cpu interrupt timing for a slave, the transmit data buffer allows back-to-b ack transmissions to occur without the slave having to time the write of its data between the transmissions. also, if no new data is written to the data buffer, the last value contained in the shift regi ster will be the next data word transmitted. bit 3 mosi spsck (cpha:cpol = 1:0) spte write to spdr 1 cpu writes byte 2 to spdr, queueing cpu writes byte 1 to spdr, clearing byte 1 transfers from transmit data 3 1 2 2 3 5 spte bit. register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 byte 2 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. byte 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 218 freescale semiconductor 19.9 resetting the spi any system reset completely resets the spi. partia l reset occurs whenever th e spi enable bit (spe) is low. whenever spe is low, the following occurs: ? the spte flag is set. ? any transmission currently in progress is aborted. ? the shift register is cleared. ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is defaul ted back to being general-purpose i/o. the following additional items are reset only by a system reset: ? all control bits in the spcr register ? all control bits in the spscr regist er (modfen, errie, spr1, and spr0) ? the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to reset all control bits when spe is set back to high fo r the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi also can be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 19.10 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 19.10.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode, the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occu rs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). (see 19.7 interrupts ). 19.10.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after the mcu exits stop mode. if stop mode is exited by reset, any transfer in progress is aborted and the spi is reset. 19.11 spi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr, $fe03) enables software to clear status bits during the break state. (see 9.7.3 sim break flag control register ). to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. i/o signals mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 219 to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a two-step read/write clearin g procedure. if software does the first step on such a bit before the break, the bit cannot change during the brea k state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the data register in break mode will not initiate a transmission nor will this data be transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 19.12 i/o signals the spi module has four i/o pins and shares three of them with a parallel i/o port. ? miso ? data received ? mosi ? data transmitted ? spsck ? serial clock ?ss ? slave select ?v ss ? clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 19.12.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmit serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a high on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. 19.12.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmit serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 19.12.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 220 freescale semiconductor when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 19.12.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. 19.5 transmission formats since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low throughout the transmission for the cpha = 1 format. see figure 19-11 . figure 19-11. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 19.13.2 spi status and control register ). note a high voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if a transmission already has begun. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 19.6.2 mode fault error ). for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the data register. (see table 19-4 ). table 19-4. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi x = don?t care byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 221 19.12.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize r adio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin. 19.13 i/o registers three registers control and monitor spi operation: ? spi control register (spcr $0010) ? spi status and control register (spscr $0011) ? spi data register (spdr $0012) 19.13.1 spi control register the spi control register: ? enables spi module interrupt requests ? selects cpu interrupt requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? configures the spsck, mosi, and miso pins as open-drain outputs ? enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the sh ift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 19-4 and figure 19-5 .) to transmit data between spi modules, the spi modules must have identical cpol bits. reset clears the cpol bit. address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 19-12. spi control register (spcr) serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 222 freescale semiconductor cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 19-4 and figure 19-5 .) to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 19-11 ). reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the dat a register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. (see 19.6.2 mode fault error ). a 1 on the ss pin does not in any way affect the state of the spi state machine. spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable bit this read/write bit enables the spi module. clear ing spe causes a partial reset of the spi (see 19.9 resetting the spi ). reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie ? spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 19.13.2 spi status and control register the spi status and control register contai ns flags to signal t he following conditions: ? receive data register full ? failure to clear sprf bit before next byte is received (overflow error) ? inconsistent logic level on ss pin (mode fault error) ? transmit data register empty the spi status and control register also c ontains bits that perform these functions: ? enable error interrupts ? enable mode fault error detection ? select master spi baud rate i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 223 sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read-only bit enables the modf and ovrf flags to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and t hen reading the spi data register. reset clears the ovrf flag. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission. in a master spi, the modf flag is set if the ss pin goes low at any time. clear the modf bit by reading the spi status and control register with modf set and then writing to the spi data register. reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if the sptie bit in the spi control register is set also. note do not write to the spi data register unless the spte bit is high. address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 r = reserved = unimplemented figure 19-13. spi status and control register (spscr) serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 224 freescale semiconductor for an idle master or idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since t he transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already ac tive slave, the load of the shift register cannot occur until the transmission is completed. this impl ies that a back-to-back write to the transmit data register is not possible. the spte i ndicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not av ailable as a general pur pose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. (see 19.12.4 ss (slave select) ). if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see 19.6.2 mode fault error ). spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 19-5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of th e clock generator module (cgm), see chapter 10 clock generator module (cgm) . bd = baud rate divisor table 19-5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 225 19.13.3 spi data register the spi data register is the read/write buffer for the receive data register and the transmit data register. writing to the spi data register writes data into the transmit data register. r eading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate buffers that can contain different values. (see figure 19-2 .) r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the buffer read is not the same as the buffer written. address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 19-14. spi data register (spdr) serial peripheral interface (spi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 226 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 227 chapter 20 timer interface module b (timb) 20.1 introduction this chapter describes the timer interface module (tim b). the timb is a 2-channel timer that provides a timing reference with input capture, output compare and pulse widt h modulation functions. figure 20-1 is a block diagram of the timb. the timb module is feature of the mc68hc908az60a only. for further information regarding timers on m68h c08 family devices, pleas e consult the hc08 timer reference manual, tim08rm/ad. 20.2 features features of the timb include: ? two input capture/output compare channels ? rising-edge, falling-edge or any-edge input capture trigger ? set, clear or toggle output compare action ? buffered and unbuffered pulse widt h modulation (pwm) signal generation ? programmable timb clock input ? 7 frequency internal bus clock prescaler selection ? external timb clock input (4 mhz maximum frequency) ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? timb counter stop and reset bits timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 228 freescale semiconductor figure 20-1. timb block diagram addr. register name bit 7654321bit 0 $0040 timb status/control register (tbsc) tof toie tstop trst 0 ps2 ps1 ps0 $0041 timb counter register high (tbcnth) bit 15 14 13 12 11 10 9 bit 8 $0042 timb counter register low (tbcntl)bit 7654321bit 0 $0043 timb counter modulo reg. high (tbmodh) bit 15 14 13 12 11 10 9 bit 8 $0044timb counter modulo reg. low (tbmodl)bit 7654321bit 0 $0045 timb ch. 0 status/control register (tbsc0) ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max $0046 timb ch. 0 register high (tbch0h) bit 15 14 13 12 11 10 9 bit 8 $0047 timb ch. 0 register low (tbch0l)bit 7654321bit 0 $0048 timb ch. 1 status/control register (tbsc1) ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max $0049 timb ch. 1 register high (tbch1h) bit 15 14 13 12 11 10 9 bit 8 $004a timb ch. 1 register low (tbch1l)bit 7654321bit 0 r= reserved figure 20-2. timb i/o register summary prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a ptf4 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd4/atd12/tbclk ptf4/tbch0 ptf5/tbch1 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a ptf5 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 229 20.3 functional description figure 20-1 shows the timb structure. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-counter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh?tbmodl, control the modulo value of the timb counter. software can read the timb counter value at any time without affecting the counting sequence. the two timb channels are programmable independently as input capture or output compare channels. 20.3.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, ptd4/atd12/tbclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the timb status and control register select the timb clock source. 20.3.2 input capture an input capture function has three basic parts: ed ge select logic, an input capture latch and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in tbsc0 through tbsc1 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the timb latches the contents of the timb counter into the timb channel registers, tbchxh?tbchxl. input captures can generate timb cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture in terrupts or by polling the status flag bit. the free-running counter contents are transferred to the timb channel register (tbchxh?tbchxl, see 20.8.5 timb channel registers ) on each proper signal transition regar dless of whether the timb channel flag (ch0f?ch1f in tbsc0?tbsc1 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register 2 bus cy cles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 20.8.5 timb channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel register (tbchxh?tbchxl). timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 230 freescale semiconductor 20.3.3 output compare with the output compare function, the timb can gener ate a periodic pulse with a programmable polarity, duration and frequency. when the counter reaches the value in the registers of an output compare channel, the timb can set, clear or toggle the chan nel pin. output compares can generate timb cpu interrupt requests. 20.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 20.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timb over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timb may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 20.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately control the output. setting the ms0b bit in timb channel 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 registers initially controls the output on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tbsc0 controls and monitors the buffered output compare function and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/t bch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 231 20.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between overflows is the period of the pwm signal. as figure 20-3 shows, the output compare value in the timb channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the timb to clear the channel pin on output compare if the polar ity of the pwm pulse is 1. program the timb to set the pin if the polarity of the pwm pulse is 0. figure 20-3. pwm period and pulse width the value in the timb counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timb counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 20.8.1 timb status and control register ). the value in the timb channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 incremen ts. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50%. 20.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 20.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the timb channel registers. an unsynchronized write to the timb channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a timb overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timb may pass the new value before it is written to the timb channel registers. ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 232 freescale semiconductor use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable ti mb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb ov erflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 20.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the li nked pair alternately control the pulse width of the output. setting the ms0b bit in timb channel 0 status and co ntrol register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the ptf4/tbch0 pin. writing to the timb channel 1 registers enables the timb channel 1 r egisters to synchronously control the pulse width at the beginning of the next pwm period. at each subs equent overflow, the timb channel registers (0 or 1) that control the pulse width are the ones written to last. tbsc0 controls and monitors the buffered pwm function, and timb channel 1 status and control regi ster (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is av ailable as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 233 20.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by setting the timb stop bit, tstop. b. reset the timb counter and prescaler by setting the timb reset bit, trst. 2. in the timb counter modulo registers (tbmo dh?tbmodl) write the value for the required pwm period. 3. in the timb channel x registers (tbchxh?tbchxl) write the value for the required pulse width. 4. in timb channel x status and control register (tbscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa (see table 20-2 ). b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level (see table 20-2 ). note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb status control register (tbsc) clear the timb stop bit, tstop. setting ms0b links channels 0 and 1 and configures t hem for buffered pwm operation. the timb channel 0 registers (tbch0h?tbch0l) initially control the bu ffered pwm output. timb status control register 0 (tbsc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output (see 20.8.4 timb channel status and control registers ). timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 234 freescale semiconductor 20.4 interrupts the following timb sources c an generate interrupt requests: ? timb overflow flag (tof) ? the tof bit is se t when the timb counter value reaches the modulo value programmed in the timb counter modulo regi sters. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt reque sts. tof and toie are in the timb status and control register. ? timb channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x timb cpu inte rrupt requests are controlled by the channel x interrupt enable bit, chxie. 20.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 20.5.1 wait mode the timb remains active after the execution of a wait instruction. in wait mode, the timb registers are not accessible by the cpu. any enabled cpu interrupt request from the timb can bring the mcu out of wait mode. if timb functions are not required during wait mode , reduce power consumption by stopping the timb before executing the wait instruction. 20.5.2 stop mode the timb is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the timb counter. timb operation resumes when the mcu exits stop mode. 20.6 timb during break interrupts a break interrupt stops the timb c ounter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state (see 9.7.3 sim break flag control register ). to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. i/o signals mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 235 20.7 i/o signals port d shares one of its pins with the timb. port f shares two of its pins with the timb. ptd4/atd12/tbclk is an external clock input to the timb prescaler. the two timb channel i/o pins are ptf4/tbch0 and ptf5/tbch1. 20.7.1 timb clock pi n (ptd4/atd12/tbclk) ptd4/atd12/tbclk is an external clock input that can be the clock source for the timb counter instead of the prescaled internal bus cl ock. select the ptd4/atd12/tbclk input by writing logic 1s to the three prescaler select bits, ps[2:0] (see 20.8.1 timb status and control register ). the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. ptd4/atd12/tbclk is available as a general-pur pose i/o pin or adc channel when not used as the timb clock input. when the ptd4/atd12/tbclk pin is the timb clock input, it is an input regardless of the state of the ddrd4 bit in data direction register d. 20.7.2 timb chan nel i/o pins (ptf5/tbch1?ptf4/tbch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptf4/tbch0 and ptf5/tbch1 can be configured as buffered output compare or buffered pwm pins. 20.8 i/o registers these i/o registers control and monitor timb operation: ? timb status and control register (tbsc) ? timb control registers (tbcnth?tbcntl) ? timb counter modulo registers (tbmodh?tbmodl) ? timb channel status and control registers (tbsc0 and tbsc1) ? timb channel registers (tbch0h?tbch0l, tbch1h?tbch1l) 20.8.1 timb status and control register the timb status and control register: ? enables timb overflow interrupts ? flags timb overflows ? stops the timb counter ? resets the timb counter ? prescales the timb counter clock 1 bus frequency ------------------------------------- t su + timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 236 freescale semiconductor tof ? timb overflow flag bit this read/write flag is set when the timb counter reaches the modulo value programmed in the timb counter modulo registers. clear tof by reading t he timb status and control register when tof is set and then writing a logic 0 to tof. if another timb overflow occurs befor e the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a logic 1 to tof has no effect. 1 = timb counter has reached modulo value 0 = timb counter has not reached modulo value toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ? timb stop bit this read/write bit stops the timb counter. countin g resumes when tstop is cleared. reset sets the tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note do not set the tstop bit before entering wait mode if the timb is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, input captures are inhibited until tstop is cleared. when using tstop to stop the timer counter, see if any timer flags are set. if a timer flag is set, it must be clea red by clearing tstop, then clearing the flag, then setting tstop again. trst ? timb reset bit setting this write-only bit resets the timb counter and the timb prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timb counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. address: $0040 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 20-4. timb status and control register (tbsc) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 237 ps[2:0] ? prescaler select bits these read/write bits select either the ptd4/atd 12/tbclk pin or one of the seven prescaler outputs as the input to the timb counter as table 20-1 shows. reset clears the ps[2:0] bits. 20.8.2 timb c ounter registers the two read-only timb counter registers contain the high and low bytes of the value in the timb counter. reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears the timb counter registers. note if tbcnth is read during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. table 20-1. prescaler selection ps[2:0] timb clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 ptd4/atd12/tbclk register name and address tbcnth ? $0041 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 register name and address tbcntl ? $0042 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 20-5. timb counter registers (tbcnth and tbcntl) timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 238 freescale semiconductor 20.8.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the modulo value, the overflow flag (tof) becomes set and the timb counter resumes counting from $0000 at the next timer clock. writing to the high byte (tbmodh) inhibits the tof bit and overflow interrupts until the low byte (tbmodl) is wr itten. reset sets the timb counter modulo registers. note reset the timb counter before writing to the timb counter modulo registers. 20.8.4 timb channel stat us and control registers each of the timb channel status and control registers: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare or pwm operation ? selects high, low or toggling output on output compare ? selects rising edge, falling edge or any e dge as the active input capture trigger ? selects output toggling on timb overflow ? selects 0% and 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation register name and address tbmodh ? $0043 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tbmodl ? $0044 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 20-6. timb counter modulo registers (tbmodh and tbmodl) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 239 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the timb counter registers matches the value in the timb channel x registers. when chxie = 1, clear chxf by reading timb channel x status and control register with chxf set, and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timb channel 0. setting ms0b disables the channel 1 status and control register and reverts tbch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation (see table 20-2 ). 1 = unbuffered output compare/pwm operation 0 = input capture operation register name and address tbsc0 ? $0045 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tbsc1 ? $0048 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved figure 20-7. timb channel status and control registers (tbsc0?tbsc1) timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 240 freescale semiconductor when elsxb:a = 00, this read/write bit selects the initial output level of the tbchx pin once pwm, input capture or output compare operation is enabled (see table 20-2 ). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port f and pin ptfx/tbchx is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 20-2 shows how elsxb and elsxa work. re set clears the elsxb and elsxa bits. note before enabling a timb channel register for input capture operation, make sure that the ptfx/tbchx pin is st able for at least two bus clocks. table 20-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 241 tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggle on timb counter overflow. note when tovx is set, a timb counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 20-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 20-8. chxmax latency 20.8.5 timb c hannel registers these read/write registers contain the captured timb counter value of the input capture function or the output compare value of the output compare function. the state of the timb channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0) reading the high byte of the timb channel x registers (tbchxh) inhibits input captures un til the low byte (tbchxl) is read. in output compare mode (msxb?msxa 0:0) writing to the high byte of the timb channel x registers (tbchxh) inhibits output compares and the chxf bit until the low byte (tbchxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module b (timb) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 242 freescale semiconductor register name and address tbch0h ? $0046 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tbch0l ? $0047 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tbch1h ? $0049 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tbch1l ? $004a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 20-9. timb channel registers (tbch0h/l?tbch1h/l) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 243 chapter 21 programmable interrupt timer (pit) 21.1 introduction this chapter describes the programmable interrupt timer (pit) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. figure 21-1 is a block diagram of the pit. for further information regarding timers on m68h c08 family devices, pleas e consult the hc08 timer reference manual, tim08rm/ad. 21.2 features features of the pit include: ? programmable pit clock input ? free-running or modulo up-count operation ? pit counter stop and reset bits 21.3 functional description figure 21-1 shows the structure of the pit. the central component of the pit is the 16-bit pit counter that can operate as a free-running counter or a mo dulo up-counter. the counter provides the timing reference for the interrupt. the pit counter modulo registers, pmodh?pmodl, control the modulo value of the counter. software can read the counter value at any time without affe cting the counting sequence. figure 21-1. pit block diagram prescaler prescaler select internal 16-bit comparator pps2 pps1 pps0 pof poie inter- timpmodh:timpmodl crst cstop 16-bit counter bus clock rupt logic programmable interrupt timer (pit) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 244 freescale semiconductor 21.4 pit counter prescaler the clock source can be one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits , pps[2:0], in the status and control register select the pit clock source. the value in the pit counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. the pit overflow flag (p of) is set when the pit counter value reaches the modulo value programmed in the pi t counter modulo registers. the pit interrupt enable bit, poie, enables pit overflow cpu interrupt requests. pof and poie are in the pit status and control register. 21.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 21.5.1 wait mode the pit remains active after the execution of a wait instruction. in wait mode the pit registers are not accessible by the cpu. any enabled cpu interrupt request from the pit can bring the mcu out of wait mode. register name bit 7654321bit 0 pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 pit counter register low (pcntl) read:bit 7654321bit 0 write: reset:00000000 pit counter modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 pit counter modulo register low (pmodl) read: bit 7654321bit 0 write: reset:11111111 =unimplemented figure 21-2. pit i/o register summary table 21-1. pit i/o register address summary register psc pcnth pcntl pmodh pmodl address $004b $004c $004d $004e $004f pit during break interrupts mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 245 if pit functions are not required during wait mode, r educe power consumption by stopping the pit before executing the wait instruction. 21.5.2 stop mode the pit is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the pit counter. pit operation resumes when the mcu exits stop mode after an external interrupt. 21.6 pit during break interrupts a break interrupt stops the pit counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state (see 9.7.3 sim break flag control register ). to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 21.7 i/o registers the following i/o registers control and monitor operation of the pit: ? pit status and control register (psc) ? pit counter registers (pcnth?pcntl) ? pit counter modulo registers (pmodh?pmodl) 21.7.1 pit status and control register the pit status and control register: ? enables pit interrupt ? flags pit overflows ? stops the pit counter ? resets the pit counter ? prescales the pit counter clock programmable interrupt timer (pit) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 246 freescale semiconductor pof ? pit overflow flag bit this read/write flag is set when the pit counter reaches the modulo val ue programmed in the pit counter modulo registers. clear pof by reading t he pit status and control register when pof is set and then writing a 0 to pof. if another pit overflow occurs before the clearing sequence is complete, then writing 0 to pof has no effect. therefore, a pof interrupt request cannot be lost due to inadvertent clearing of pof. reset clears th e pof bit. writing a 1 to pof has no effect. 1 = pit counter has reached modulo value 0 = pit counter has not reached modulo value poie ? pit overflow interrupt enable bit this read/write bit enables pit overflow interr upts when the pof bit becomes set. reset clears the poie bit. 1 = pit overflow interrupts enabled 0 = pit overflow interrupts disabled pstop ? pit stop bit this read/write bit stops the pit counter. counting resumes when pstop is cleared. reset sets the pstop bit, stopping the pit counter until software clears the pstop bit. 1 = pit counter stopped 0 = pit counter active note do not set the pstop bit before entering wait mode if the pit is required to exit wait mode. prst ? pit reset bit setting this write-only bit resets the pit counter and the pit prescaler. setting prst has no effect on any other registers. counting resumes from $0000. prst is cleared automatically after the pit counter is reset and always reads as logic zero. reset clears the prst bit. 1 = prescaler and pit counter cleared 0 = no effect note setting the pstop and prst bits simultaneously stops the pit counter at a value of $0000. pps[2:0] ? prescaler select bits these read/write bits select one of the seven pres caler outputs as the input to the pit counter as table 21-2 shows. reset clears the pps[2:0] bits. address: $004b bit 7654321bit 0 read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 = unimplemented figure 21-3. pit status and control register (psc) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 247 21.7.2 pit count er registers the two read-only pit counter registers contain the high and low bytes of the value in the pit counter. reading the high byte (pcnth) latches the contents of the low byte (pcntl) into a buffer. subsequent reads of pcnth do not affect the latched pcntl value until pcntl is read. reset clears the pit counter registers. setting the pit reset bit (prst) also clears the pit counter registers. note if you read pcnth during a break interrupt, be sure to unlatch pcntl by reading pcntl before exiting the break interrupt. otherwise, pcntl retains the value latched during the break. table 21-2. prescaler selection pps[2:0] pit clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 internal bus clock 64 address: $004c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 address: $004d bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 21-4. pit counter registers (pcnth?pcntl) programmable interrupt timer (pit) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 248 freescale semiconductor 21.7.3 pit counter modulo registers the read/write pit modulo registers contain the modulo value for the pit counter. when the pit counter reaches the modulo value the overflow flag (pof) becomes set and the pit counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (pmodh) inhibits the pof bit and overflow interrupts until the low byte (pmodl) is written. reset sets the pit counter modulo registers. note reset the pit counter before writing to the pit counter modulo registers. address: $004e:$004f bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 address: $004e:$004f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 21-5. pit counter modulo registers (pmodh?pmodl) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 249 chapter 22 input/output ports 22.1 introduction on the mc68hc908az60a and 64-pin mc68hc908as60a, fifty bidirectional input/output (i/o) form seven parallel ports. on the52-pin mc68hc908as60a, fo rty bidirectional input/output (i/o) form six parallel ports. all i/o pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. register name bit 7654321bit 0 $0000 port a data register (pta) pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 $0001 port b data register (ptb) ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 $0002 port c data register (ptc) 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 $0003 port d data register (ptd) ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 $0004 data direction register a (ddra) ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 $0005 data direction register b (ddrb) ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 $0006 data direction register c (ddrc) mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 $0007 data direction register d (ddrd) ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 $0008 port e data register (pte) pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 $0009 port f data register (ptf) 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 $000a port g data register (ptg) 00000ptg2ptg1ptg0 $000b port h data register (pth) 000000pth1pth0 $000c data direction register e (ddre) ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 $000d data direction register f ( ddrf) 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 $000e data direction register g (ddrg) 00000ddrg2ddrg1ddrg0 $000fdata direction register h (ddrh)000000ddrh1ddrh0 figure 22-1. i/o port register summary input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 250 freescale semiconductor 22.2 port a port a is an 8-bit general-purpose bidirectional i/o port. 22.2.1 port a data register the port a data register contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. 22.2.2 data dir ection register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 22-4 shows the port a i/o logic. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 22-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 22-3. data direction register a (ddra) port a mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 251 figure 22-4. port a i/o circuit when bit ddrax is a logic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-1 summarizes the operation of the port a pins. table 22-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x input, hi-z ddra[7:0] pin pta[7:0] (1) 1 x output ddra[7:0] pta[7:0] pta[7:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 252 freescale semiconductor 22.3 port b port b is an 8-bit special function port that shares all of its pins with the analog-to-digital converter. 22.3.1 port b data register the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. atd[7:0] ? adc channels ptb7/atd7?ptb0/atd0 are eight of the analog-t o-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptb7/atd7?ptb0/atd0 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the dat a direction for this bit is programmed as an input. otherwise, the data will reflect the value in the data latch. (see chapter 26 analog-to-digital converter (adc) ). data direction register b (ddrb) does not affect the data direction of port b pins that are being used by the adc. however, the ddrb bits always determine whether reading port b returns to the states of the latches or 0. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative functions: atd7 atd6 atd5 atd4 atd3 atd2 atd1 atd0 figure 22-5. port b data register (ptb) port b mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 253 22.3.2 data dir ection register b data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 22-7 shows the port b i/o logic. figure 22-7. port b i/o circuit when bit ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 22-6. data direction register b (ddrb) table 22-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x input, hi-z ddrb[7:0] pin ptb[7:0] (1) 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 254 freescale semiconductor 22.4 port c port c is an 6-bit general-purpose bidirectional i/o port. note that ptc5 is only available on 64-pin package options. 22.4.1 port c data register the port c data register contains a data latch for each of the six port c pins. ptc[5:0] ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data (5:0). mclk ? system clock bit the system clock is driven out of ptc2 when enabled by mclken bit in ptcddr7. 22.4.2 data dir ection register c data direction register c determines whether each por t c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. mclken ? mclk enable bit this read/write bit en ables mclk to be an output signal on ptc2. if mclk is enabled, ddrc2 has no effect. reset clears this bit. 1 = mclk output enabled 0 = mclk output disabled address: $0002 bit 7654321bit 0 read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r r reset: unaffected by reset r= reserved alternative functions: mclk figure 22-8. port c data register (ptc) address: $0006 bit 7654321bit 0 read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset:00000000 r= reserved figure 22-9. data direction register c (ddrc) port c mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 255 ddrc[5:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 22-10 shows the port c i/o logic. figure 22-10. port c i/o circuit when bit ddrcx is a logic 1, r eading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-3 summarizes the operation of the port c pins. table 22-3. port c pin functions bit value ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc[2] pin ptc2 1 2 output ddrc[2] 0 ? 0 x input, hi-z ddrc[5:0] pin ptc[5:0] (1) 1 x output ddrc[5:0] ptc[5:0] ptc[5:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 256 freescale semiconductor 22.5 port d port d is an 8-bit general-purpose i/o port. note th at ptd7 is only availabl e on 64-pin package options. 22.5.1 port d data register port d is a 8-bit special function port that shares seven of its pins with the analog to digital converter and two with the timer interface modules. ptd[7:0] ? port d data bits ptd[7:0] are read/write, software programmable bits . data direction of ptd[7:0] pins are under the control of the corresponding bit in data direction register d. atd[14:8] ? adc channel status bits ptd6/atd14/taclk?ptd0/atd8 are seven of the 15 analog-to-digital converter channels. the adc channel select bits, ch[4:0], determine whether the ptd6/atd14/taclk?ptd0/atd8 pins are adc channels or general-purpose i/o pins. if an adc channel is selected and a read of this corresponding bit in the port b data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. otherwise, the data will re flect the value in the data latch. (see chapter 26 analog-to-digital converter (adc) ). note data direction register d (ddrd) does not affect the data direction of port d pins that are being used by the tima or timb. however, the ddrd bits always determine whether reading port d returns the states of the latches or a 0. taclk/tbclk ? timer clock input bit the ptd6/atd14/taclk pin is the external clock input for the tima. the ptd4/atd12/tbclk pin is the external clock input for the timb. the prescaler select bits, ps[2:0], select ptd6/atd14/taclk or ptd4/atd12/tbclk as the tim clock input. (see 25.8.4 tima channel status and control registers and 20.8.4 timb channel status and control registers ). when not selected as the tim clock, ptd6/atd14/taclk and ptd4/atd12/tbclk are available for general-purpose i/o. while taclk/tbclk are selected correspon ding ddrd bits have no effect. address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative functions: atd14 atd13 atd12 atd11 atd10 atd9 atd8 taclk tbclk figure 22-11. port d data register (ptd) port d mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 257 22.5.2 data dir ection register d data direction register d determines whether each por t d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. ddrd[7:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. figure 22-13 shows the port d i/o logic. figure 22-13. port d i/o circuit when bit ddrdx is a logic 1, r eading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-4 summarizes the operation of the port d pins. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 22-12. data direction register d (ddrd) table 22-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x input, hi-z ddrd[7:0] pin ptd[7:0] (1) 1 x output ddrd[7:0] pt d[7:0] ptd[7:0] x = don?t care hi-z = high impedance 1. writing affects dat a register, but does not affect input. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 258 freescale semiconductor 22.6 port e port e is an 8-bit special function port that shares tw o of its pins with the timer interface module (tima), two of its pins with the serial communications interf ace module (sci), and four of its pins with the serial peripheral interface module (spi). 22.6.1 port e data register the port e data register contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software programmable bits . data direction of each port e pin is under the control of the corresponding bit in data direction register e. spsck ? spi serial clock bit the pte7/spsck pin is the serial clock input of an spi slav e module and serial clock output of an spi master module. when the spe bit is clear, the pt e7/spsck pin is availabl e for general-purpose i/o. (see 19.13.1 spi control register ). mosi ? master out/slave in bit the pte6/mosi pin is the master out/slave in term inal of the spi module. when the spe bit is clear, the pte6/mosi pin is available for general-purpose i/o. miso ? master in/slave out bit the pte5/miso pin is the master in/slave out te rminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pt e5/miso pin is available for general-purpose i/o. (see 19.13.1 spi control register ). ss ? slave select bit the pte4/ss pin is the slave select input of the spi module. when the spe bit is clear, or when the spi master bit, spmstr, is set and modfen bit is low, the pte4/ss pin is available for general-purpose i/o. (see 19.12.4 ss (slave select) ). when the spi is enabled as a slave, the ddrf0 bit in data direction register e (ddre) has no effect on the pte4/ss pin. note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 22-5 ). address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: spsck mosi miso ss tach1 tach0 rxd txd figure 22-14. port e data register (pte) port e mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 259 tach[1:0] ? timer channel i/o bits the pte3/tach1?pte2/tach0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether t he pte3/tach1?pte2/tach0 pins are timer channel i/o pins or general-purpose i/o pins. (see 25.8.4 tima channel status and control registers ). note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 22-5 ). rxd ? sci receive data input bit the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. (see 18.8.1 sci control register 1 ). txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. (see 18.8.1 sci control register 1 ). note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 22-5 ). 22.6.2 data dir ection register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] ? data direction register e bits these read/write bits contro l port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 22-15. data direction register e (ddre) input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 260 freescale semiconductor figure 22-16 shows the port e i/o logic. figure 22-16. port e i/o circuit when bit ddrex is a logic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-5 summarizes the operation of the port e pins. 22.7 port f port f is a 7-bit special function port that shares four of its pins with the timer interface module (tima-6) and two of its pins with the timer interface module (timb) on the mc68hc908az60a. note that ptf4, ptf5 and ptf6 are only available on 64-pin package options. table 22-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x input, hi-z ddre[7:0] pin pte[7:0] (1) 1 x output ddre[7:0] pte[7:0] pte[7:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus port f mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 261 22.7.1 port f data register the port f data register contains a data latch for each of the seven port f pins. ptf[6:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction re gister f. reset has no effect on ptf[6:0]. tach[5:2] ? timer a channel i/o bits the ptf3?ptf0/tach2 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptf3?p tf0/tach2 pins are timer channel i/o pins or general-purpose i/o pins. (see 25.8.1 tima status and control register ). tbch[1:0] ? timer b channel i/o bits the ptf5/tbch1?ptf4/tbch0 pins are the timb i nput capture/output compare pins. the edge/level select bits, elsxb:elsxa, dete rmine whether the ptf5/tbch1?ptf4/tbch0 pins are timer channel i/o pins or general-purpose i/o pins. (see 20.8.1 timb status and control register ). note data direction register f (ddrf) does not affect the data direction of port f pins that are being used by the ti m. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. (see table 22-6 ). 22.7.2 data dir ection register f data direction register f determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the correspondi ng port f pin; a logic 0 di sables the output buffer. address: $0009 bit 7654321bit 0 read: 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r reset: unaffected by reset alternative function: tbch1 tbch0 tach5 tach4 tach3 tach2 r= reserved figure 22-17. port f data register (ptf) address: $000d bit 7654321bit 0 read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r reset:00000000 r= reserved figure 22-18. data direction register f (ddrf) input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 262 freescale semiconductor ddrf[6:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[6:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note avoid glitches on port f pins by writ ing to the port f data register before changing data direction regist er f bits from 0 to 1. figure 22-19 shows the port f i/o logic. figure 22-19. port f i/o circuit when bit ddrfx is a logic 1, r eading address $0009 read s the ptfx data latch. when bit ddrfx is a logic 0, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-6 summarizes the operation of the port f pins. table 22-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x input, hi-z ddrf[6:0] pin ptf[6:0] (1) 1 x output ddrf[6:0] ptf[6:0] ptf[6:0] x = don?t care hi-z = high impedance 1. writing affects data register , but does not affect input. read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus port g mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 263 22.8 port g port g is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (kbd). note that port g is only avai lable on 64-pin package options. 22.8.1 port g data register the port g data register contains a data la tch for each of the three port g pins. ptg[2:0] ? port g data bits these read/write bits are software programmable. data direction of each port g pin is under the control of the corresponding bit in data direction regi ster g. reset has no effect on ptg[2:0]. kbd[2:0] ? keyboard wakeup pins the keyboard interrupt enable bits, kbie[2:0], in the keyboard interrupt control register, enable the port g pins as external interrupt pins (see chapter 24 keyboard module (kbi) ). enabling an external interrupt pin will override the corresponding ddrgx. 22.8.2 data dir ection register g data direction register g determi nes whether each port g pin is an input or an output. writing a logic 1 to a ddrg bit enables the output buffer for the corresponding port g pin; a logic 0 disables the output buffer. address: $000a bit 7654321bit 0 read:00000 ptg2 ptg1 ptg0 write:rrrrr reset: unaffected by reset alternative function: kbd2 kbd1 kbd0 r= reserved figure 22-20. port g data register (ptg) address: $000e bit 7654321bit 0 read:00000 ddrg2 ddrg1 ddrg0 write:rrrrr reset:00000000 r= reserved figure 22-21. data direction register g (ddrg) input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 264 freescale semiconductor ddrg[2:0] ? data direction register g bits these read/write bits control port g data direction. reset clears ddrg[2:0], conf iguring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note avoid glitches on port g pins by writing to the port g data register before changing data direction regist er g bits from 0 to 1. figure 22-22 shows the port g i/o logic. figure 22-22. port g i/o circuit when bit ddrgx is a logic 1, reading address $000a reads the ptgx data latch. when bit ddrgx is a logic 0, reading address $000a reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-7 summarizes the operation of the port g pins. table 22-7. port g pin functions ddrg bit ptg bit i/o pin mode accesses to ddrg accesses to ptg read/write read write 0 x input, hi-z ddrg[2:0] pin ptg[2:0] (1) 1 x output ddrg[2:0] ptg[2:0] ptg[2:0] x = don?t care hi-z = high impedance 1. writing affects data register , but does not affect input. read ddrg ($000e) write ddrg ($000e) reset write ptg ($000a) read ptg ($000a) ptgx ddrgx ptgx internal data bus port h mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 265 22.9 port h port h is a 2-bit special function port that shares all of its pins with the keyboard interrupt module (kbd). note that port h is only available on 64-pin package options. 22.9.1 port h data register the port h data register contains a data latch for each of the two port h pins. pth[1:0] ? port h data bits these read/write bits are software programmable. data direction of each port h pin is under the control of the corresponding bit in data direction regi ster h. reset has no effect on pth[1:0]. kbd[4:3] ? keyboard wake-up pins the keyboard interrupt enable bits, kbie[4:3], in the keyboard interrupt control register, enable the port h pins as external interrupt pins (see chapter 24 keyboard module (kbi) ). 22.9.2 data dir ection register h data direction register h determines whether each por t h pin is an input or an output. writing a logic 1 to a ddrh bit enables the output buffer for the corresponding port h pin; a logic 0 disables the output buffer. ddrh[1:0] ? data direction register h bits these read/write bits control port h data direction. reset clears ddrg[1:0], configuring all port h pins as inputs. 1 = corresponding port h pin configured as output 0 = corresponding port h pin configured as input note avoid glitches on port h pins by writin g to the port h data register before changing data direction regist er h bits from 0 to 1. address: $000b bit 7654321bit 0 read:000000 pth1 pth0 write:rrrrrr reset: unaffected by reset alternative function: kbd4 kbd3 r= reserved figure 22-23. port h data register (pth) address: $000f bit 7654321bit 0 read:000000 ddrh1 ddrh0 write:rrrrrr reset:00000000 r= reserved figure 22-24. data direction register h (ddrh) input/output ports mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 266 freescale semiconductor figure 22-25 shows the port h i/o logic. figure 22-25. port h i/o circuit when bit ddrhx is a logic 1, r eading address $000b reads the pthx data latch. when bit ddrhx is a logic 0, reading address $000b reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 22-8 summarizes the operation of the port h pins. table 22-8. port h pin functions ddrh bit pth bit i/o pin mode accesses to ddrh accesses to pth read/write read write 0 x input, hi-z ddrh[1:0] pin pth[1:0] (1) 1 x output ddrh[1:0] pth[1:0] pth[1:0] x = don?t care hi-z = high impedance 1. writing affects data register, but does not affect input. read ddrh ($000f) write ddrh ($000f) reset write pth ($000b) read pth ($000b) pthx ddrhx pthx internal data bus mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 267 chapter 23 mscan controller (mscan08) 23.1 introduction the mscan08 is the specific implementation of the mscan concept targeted for the freescale m68hc08 microcontroller family. the module is a communication controller implement ing the can 2.0 a/b protocol as defined in the bosch specification dated september 1991. the can protocol was primarily, but not exclusivel y, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (emi) environment of a vehicle, cost-effectiveness and required bandwidth. mscan08 utilizes an advanced buffer arrangement, resu lting in a predictable real-time behavior, and simplifies the application software. the mscan08 is only avail able on the mc68hc908az60a. 23.2 features basic features of the mscan08 are: ? modular architecture ? implementation of the can protocol ? version 2.0a/b ? standard and extended data frames. ? 0?8 bytes data length. ? programmable bit rate up to 1 mbps depending on the actual bit timing and the clock jitter of the pll ? support for remote frames ? double-buffered receive storage scheme ? triple-buffered transmit storage scheme with in ternal prioritisation using a ?local priority? concept ? flexible maskable identifier filter supports altern atively one full size extended identifier filter or two 16-bit filters or four 8-bit filters ? programmable wakeup functionality with integrated low-pass filter ? programmable loop-back mode supports self-test operation ? separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus off) ? programmable mscan08 clock source either cpu bus clock or crystal oscillator output ? programmable link to on-chip timer interface module (timb) for time -stamping and network synchronization ? low-power sleep mode mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 268 freescale semiconductor 23.3 external pins the mscan08 uses two external pins, one input (rxcan) and one output (txcan). the txcan output pin represents the logic level on the can: 0 is fo r a dominant state, and 1 is for a recessive state. a typical can system with mscan08 is shown in figure 23-1 . figure 23-1. the can system each can station is connected physically to th e can bus lines through a transceiver chip. the transceiver is capable of driving the large current needed for the can and has current protection against defected can or defected stations. 23.4 message storage mscan08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 23.4.1 background modern application layer software is bui lt under two fundamental assumptions: 1. any can node is able to send out a stream of scheduled messages without releasing the bus between two messages. such nodes will arbitrate for the bus right after sending the previous message and will only release the bu s in case of lost arbitration. 2. the internal message queue within any can node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. c a n bus can controller (mscan08) transceiver can node 1 can station 1 can node 2 can node n can_l can_h txcan rxcan mcu message storage mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 269 above behavior cannot be achieved with a single transmi t buffer. that buffer must be reloaded right after the previous message has been sent. this loading proc ess lasts a definite amount of time and has to be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the cpu. problems may arise if the sending of a message would be finished just while t he cpu re-loads the second buffer. in that case, no buffer would then be ready for transmi ssion and the bus would be released. at least three transmit buffers are required to meet the first of the above requirements under all circumstances. the mscan08 has three transmit buffers. the second requirement calls for some sort of inte rnal prioritisation which the mscan08 implements with the ?local priority? concept described in 23.4.2 receive structures . 23.4.2 receive structures the received messages are stored in a 2-stage input first in first out (fifo). the two message buffers are mapped using a ping pong arrangement into a single memory area (see figure 23-2 ). while the background receive buffer (rxbg) is exclusively asso ciated to the mscan08, the foreground receive buffer (rxfg) is addressable by the cpu08. this scheme simplifies the handl er software, because only one address area is applicable for the receive process. both buffers have a size of 13 bytes to store the ca n control bits, the identifier (standard or extended), and the data content (for details, see 23.12 programmer?s model of message storage ). the receiver full flag (rxf ) in the mscan08 receiver flag register (crflg) (see 23.13.5 mscan08 receiver flag register (crflg) ), signals the status of the foreground receive buffer. when the buffer contains a correctly received message with matching identifier, this flag is set. on reception, each message is checked to see if it passes the filter (for details see 23.5 identifier acceptance filter ) and in parallel is written into rxbg. the mscan08 copies the content of rxbg into rxfg (1) , sets the rxf flag, and generates a receive interrupt to the cpu (2) . the user?s receive handler has to read the received message from rxfg and to re set the rxf flag to acknowledge the interrupt and to release the foreground buffer. a new message which can follow immediately af ter the ifs field of the can frame, is received into rxbg. the overwr iting of the background buffer is independent of the identifier filter function. when the mscan08 module is transmitting, the mscan08 receives its own messages into the background receive buffer, rxbg. it does not over write rxfg, generate a receive interrupt or acknowledge its own messages on the can bus. the ex ception to this rule is in loop-back mode (see 23.13.2 mscan08 module control register 1 ), where the mscan08 treats its own messages exactly like all other incoming messages. the mscan08 receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan08 must be prepared to become receiver. 1. only if the rxf flag is not set. 2. the receive interrupt will occur only if not masked. a polling scheme can be applied on rxf also. mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 270 freescale semiconductor an overrun condition occurs when both the for eground and the background receive message buffers are filled with correctly received messages with acc epted identifiers and another message is correctly received from the bus with an accepted identifi er. the latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. the mscan08 is still able to transmit messages with both receive message buffers f illed, but all incoming messages are discarded. figure 23-2. user model for message buffer organization 23.4.3 transmit structures the mscan08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. the three buffers are arranged as shown in figure 23-2 . all three buffers have a 13-byte data structure si milar to the outline of the receive buffers (see 23.12 programmer?s model of message storage ). an additional transmit buffer pr iority register (tbpr) contains an 8-bit ?local priority? field (prio) (see 23.12.5 transmit buffer priority registers ). rxfg rxbg tx0 rxf txe prio tx1 txe prio tx2 txe prio mscan08 cpu08 ibus identifier acceptance filter mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 271 to transmit a message, the cpu08 has to identify an av ailable transmit buffer which is indicated by a set transmit buffer empty (txe) flag in the ms can08 transmitter flag register (ctflg) (see 23.13.7 mscan08 transmitter flag register ). the cpu08 then stores the identifier, the control bits and the data content into one of the transmit buffers. finally, the buffer has to be flagged ready for transmission by clearing the txe flag. the mscan08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the txe flag. a transmit interrupt is generated (1) when txe is set and can be used to drive the application software to re-load the buffer. in case more than one buffer is scheduled for trans mission when the can bus becomes available for arbitration, the mscan08 uses the local priority setti ng of the three buffers for prioritisation. for this purpose, every transmit buffer has an 8-bit local prio rity field (prio). the application software sets this field when the message is set up. the local priority refl ects the priority of this particular message relative to the set of messages being emitted from this node. th e lowest binary value of the prio field is defined as the highest priority. the internal scheduling process takes place whenever th e mscan08 arbitrates for the bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the appl ication software, it may become necessary to abort a lower priority message being set up in one of the th ree transmit buffers. as messages that are already under transmission cannot be aborted, the user ha s to request the abort by setting the corresponding abort request flag (abtrq) in the transmission contro l register (ctcr). the mscan08 will then grant the request, if possible, by setting the corresponding abort request acknowledge (abtak) and the txe flag in order to release the buffer and by generating a transmit interrupt. the transmit interrupt handler software can tell from the setting of the abtak flag whether the message was actually aborted (abtak = 1) or sent (abtak = 0). 23.5 identifier acceptance filter the identifier acceptance registers (cidar0-3) def ine the acceptance patterns of the standard or extended identifier (id10-id0 or id28-id0). any of these bits can be marked ?don?t care? in the identifier mask registers (cidmr0-3). a filter hit is indicated to the application on softw are by a set rxf (receive buffer full flag, see 23.13.5 mscan08 receiver flag register (crflg) ) and two bits in the identifier acceptance control register (see 23.13.9 mscan08 identifier acceptance control register ). these identifier hit flags (idhit1-0) clearly identify the filter section that caused the acce ptance. they simplify the application software?s task to identify the cause of the receiver interrupt. in case that more than one hit occurs (two or more filters match) the lower hit has priority. a very flexible programmable generic identifier acceptance filter has be en introduced to reduce the cpu interrupt loading. the filter is programmable to operate in four different modes: ? single identifier acceptance filter , each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the can frame: rtr, ide, srr or b) the 11 bits of the standard identifier plus the rtr and ide bits of can 2.0a/b messages. this mode implements a single filter for a full length can 2.0b compliant extended identifier. figure 23-3 shows how the 32-bit filter bank (cidar0-3, cidmr0-3) produces a filter 0 hit. 1. the transmit interrupt will occur only if not ma sked. a polling scheme can be applied on txe also. mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 272 freescale semiconductor ? two identifier acceptance filters, each to be appl ied to a) the 14 most significant bits of the extended identifier plus the srr and the ide bits of can2.0b messages, or b) the 11 bits of the identifier plus the rtr and ide bits of can 2.0a/b messages. figure 23-4 shows how the 32-bit filter bank (cidar0-3, cidmr0-3) produces filter 0 and 1 hits. ? four identifier acceptance filters, each to be applied to the first eight bits of the identifier. this mode implements four independent filters for the first eight bits of a can 2.0a/b compliant standard identifier. figure 23-5 shows how the 32-bit filter bank (cidar0-3, cidmr0-3) produces filter 0 to 3 hits. ? closed filter. no can message will be copied into the foreground buffer rxfg, and the rxf flag will never be set. figure 23-3. single 32-bit maskable identifier acceptance filter figure 23-4. dual 16-bit maskable acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 0 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 0 hit) ac7 ac0 cidar2 am7 am0 cidmr2 ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 1 hit) identifier acceptance filter mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 273 figure 23-5. quadruple 8-bit maskable acceptance filters ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 274 freescale semiconductor 23.6 interrupts the mscan08 supports four interrupt vectors mapped on to eleven different interrupt sources, any of which can be individually masked (for details see 23.13.5 mscan08 receiver flag register (crflg) , to 23.13.8 mscan08 transmitter control register ). ? transmit interrupt : at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for tr ansmission. the txe flags of the empty message buffers are set. ? receive interrupt : a message has been received successfully and loaded into the foreground receive buffer. this interrupt will be emitted im mediately after receiving the eof symbol. the rxf flag is set. ? wakeup interrupt : an activity on the can bus occurred during mscan08 internal sleep mode or power-down mode (provid ed slpak = wupie = 1). ? error interrupt : an overrun, error, or warning conditi on occurred. the receiver flag register (crflg) will indicate one of the following conditions: ? overrun: an overrun condition as described in 23.4.2 receive structures , has occurred. ? receiver warning : the receive error counter has reached the cpu warning limit of 96. ? transmitter warning : the transmit error counter has reached the cpu warning limit of 96. ? receiver error passive : the receive error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. ? transmitter error passive : the transmit error counter has exceeded the error passive limit of 127 and mscan08 has gone to error passive state. ? bus off : the transmit error counter has exceeded 255 and mscan08 has gone to bus off state. 23.6.1 interrupt acknowledge interrupts are directly associated with one or more status flags in either the mscan08 receiver flag register (crflg) or the mscan08 transmitter flag register (ctflg). interrupts are pending as long as one of the corresponding flags is set. the flags in the above registers must be reset within the interrupt handler in order to handshake the interrupt. the flags are reset through writing a ?1? to the corresponding bit position. a flag cannot be cleared if the respective condi tion still prevails. note bit manipulation instructions (bset) shall not be used to clear interrupt flags. protocol violation protection mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 275 23.6.2 interrupt vectors the mscan08 supports four interrupt vectors as shown in table 23-1 . the vector addresses and the relative interrupt priority are dependent on the chip integration and to be defined. 23.7 protocol violation protection the mscan08 will protect the user from accidenta lly violating the can prot ocol through programming errors. the protection logic implements the following features: ? the receive and transmit error counters ca nnot be written or otherwise manipulated. ? all registers which control the configuratio n of the mscan08 can not be modified while the mscan08 is on-line. the sftres bit in t he mscan08 module control register (see 23.13.1 mscan08 module control register 0 ) serves as a lock to protect the following registers: ? mscan08 module control register 1 (cmcr1) ? mscan08 bus timing register 0 and 1 (cbtr0 and cbtr1) ? mscan08 identifier acceptance control register (cidac) ? mscan08 identifier acceptance registers (cidar0?3) ? mscan08 identifier mask registers (cidmr0?3) ? the txcan pin is forced to recessive when t he mscan08 is in any of the low power modes. 23.8 low power modes in addition to normal mode, the mscan08 has three modes with reduced power consumption: sleep, soft reset and power down modes. in sleep and soft reset mode, power consumption is reduced by stopping all clocks except those to access the registers. in power down mode, all clocks are stopped and no power is consumed. the wait and stop instructions put the mcu in lo w power consumption stand-by modes. summarizes the combinations of mscan08 and cpu modes. a particular combination of modes is entered for the given settings of the bits slpak and sftres. for a ll modes, an mscan wake -up interrupt can occur only if slpak=wupie=1. table 23-1. mscan08 interrupt vector addresses function source local mask global mask wakeup wupif wupie i bit error interrupts rwrnif rwrnie twrnif twrnie rerrif rerrie terrif terrie boffif boffie ovrif ovrie receive rxf rxfie tr a n s m i t txe0 txeie0 txe1 txeie1 txe2 txeie2 mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 276 freescale semiconductor . 23.8.1 mscan08 sleep mode the cpu can request the mscan08 to enter the lo w-power mode by asserting the slprq bit in the module configuration register (see figure 23-6 ). the time when the mscan08 enters sleep mode depends on its activity: ? if it is transmitting, it continues to transmit un til there is no more message to be transmitted, and then goes into sleep mode ? if it is receiving, it waits for the end of this message and then goes into sleep mode ? if it is neither transmitting or receivi ng, it will immediately go into sleep mode note the application software must avoid setting up a transmission (by clearing or more txe flags) and immediately request sleep mode (by setting slprq). it then depends on the exact sequence of operations whether mscan08 starts transmitting or goes into sleep mode directly. figure 23-6. sleep request/acknowledge cycle table 23-2. mscan08 versus cpu operating modes mscan mode cpu mode stop wait or run power down slpak = x (1) sftres = x 1. ?x? means don?t care. sleep slpak = 1 sftres = 0 soft reset slpak = 0 sftres = 1 normal slpak = 0 sftres = 0 mscan08 running slprq = 0 slpak = 0 sleep request slprq = 1 slpak = 0 mscan08 sleeping slprq = 1 slpak = 1 mcu mscan08 mcu or mscan08 low power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 277 during sleep mode, the slpak flag is set. the app lication software should us e slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode, the mscan08 stops its internal clocks. however, clocks to allow register ac cesses still run. if the mscan08 is in buss-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. the txcan pin stays in recessive state. if rxf=1, the message can be r ead and rxf can be cleared. copying of rxgb into rxfg doesn?t take place while in sleep mode. it is possible to access the transmit buffers and to clear the txe flags. no message abort takes place while in sleep mode. the mscan08 leaves sleep mode (wake-up) when: ? bus activity occurs or ? the mcu clears the slprq bit or ? the mcu sets the sftres bit note the mcu cannot clear the slprq bit before the mscan08 is in sleep mode (slpak=1). after wake-up, the mscan08 waits for 11 consecutive recessive bits to synchr onize to the bus. as a consequence, if the mscan08 is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions are executed upon wake -up: copying of rxbg into rxfg, message aborts and message transmissions. if t he mscan08 is still in bus-off state after sleep mode was left, it continues counting the 128*11 consec utive recessive bits. 23.8.2 mscan08 soft reset mode in soft reset mode, the mscan08 is stopped. regist ers can still be accessed. this mode is used to initialize the module configuration, bit timing and the can message filter. see 23.13.1 mscan08 module control register 0 for a complete description of the soft reset mode. when setting the sftres bit, the mscan08 imm ediately stops all ongoing transmissions and receptions, potentially causi ng can protocol violations. note the user is responsible to take care that the mscan08 is not active when soft reset mode is entered. the recommended procedure is to bring the mscan08 into sleep mode before the sftres bit is set. 23.8.3 mscan08 power down mode the mscan08 is in power down mode when the cpu is in stop mode. when entering the power down mode, the mscan08 immediately stops all ongoing transmissions and receptions, potentially causi ng can protocol violations. note the user is responsible to take care that the mscan08 is not active when power down mode is entered. the recommended procedure is to bring the mscan08 into sleep mode before the stop instruction is executed. to protect the can bus system from fatal consequenc es of violations to the above rule, the mscan08 drives the txcan pin into recessive state. mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 278 freescale semiconductor in power down mode, no registers can be accessed. mscan08 bus activity can wake the mcu from cp u stop/mscan08 power-down mode. however, until the oscillator starts up and synchronisation is achi eved the mscan08 will not respond to incoming data. 23.8.4 cpu wait mode the mscan08 module remains active during cpu wait mode. the mscan08 will stay synchronized to the can bus and generates transmit, receive, and error interrupts to the cpu, if enabled. any such interrupt will bring the mcu out of wait mode. 23.8.5 programmable wakeup function the mscan08 can be programmed to apply a low-pass filter function to the rxcan input line while in internal sleep mode (see information on control bit wupm in 23.13.2 mscan08 module control register 1 ). this feature can be used to protect the msca n08 from wake-up due to short glitches on the can bus lines. such glitches can result from el ectromagnetic inference within noisy environments. 23.9 timer link the mscan08 will generate a timer signal whenever a valid frame has been received. because the can specification defines a frame to be valid if no erro rs occurred before the eof field has been transmitted successfully, the timer signal will be generated right after the eof. a pulse of one bit time is generated. as the mscan08 receiver engine also receives the fram es being sent by itself, a timer signal also will be generated after a successful transmission. the previously described timer signal can be routed into the on-chip timer interface module (tim).this signal is connected to the timer n channel m input (1) under the control of the timer link enable (tlnken) bit in the cmcr0. after timer n has been programmed to capture rising edge events, it can be used under software control to generate 16-bit time stamps which can be stored with the received message. 23.10 clock system figure 23-7 shows the structure of the mscan08 clock generation circuitry and its interaction with the clock generation module (cgm). with this flexible clocking scheme the mscan08 is able to handle can bus rates ranging from 10 kbps up to 1 mbps. 1. the timer channel being used for th e timer link is integration dependent. clock system mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 279 figure 23-7. clocking scheme the clock source bit (clksrc) in the mscan08 module control register (cmcr1) (see 23.13.1 mscan08 module control register 0 ) defines whether the mscan08 is connected to the output of the crystal oscillator or to the pll output. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. note if the system clock is generated from a pll, it is recommended to select the crystal clock source rather than th e system clock source due to jitter considerations, especially at faster can bus rates. a programmable prescaler is used to generate out of the mscan08 clock the time quanta (tq) clock. a time quantum is the atomic unit of time handled by the mscan08. a bit time is subdivided into three segments (1) (see figure 23-8 ). ? sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section. ? time segment 1: this segm ent includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the para meter tseg1 to consist of 4 to 16 time quanta. 1. for further explanation of the underlying concep ts please refer to iso/dis 11 519-1, section 10.3. pll 2 mscan08 prescaler (1 .. 64) osc cgmxclk 2 cgmout (to sim) cgm 2 clksrc mscanclk (2 * bus freq.) bcs f tq = f mscanclk presc value mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 280 freescale semiconductor ? time segment 2: this segment represent s phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. the synchronization jump width (sjw) can be programm ed in a range of 1 to 4 time quanta by setting the sjw parameter. the above parameters can be set by programming the bus timing registers, cbtr0?cbtr1, see 23.13.3 mscan08 bus timing register 0 and 23.13.4 mscan08 bus timing register 1 ). note it is the user?s responsibility to make su re that the bit timing settings are in compliance with the can standard, table 23-8 gives an overview on the can conforming segment settings and the related parameter values. figure 23-8. segments within the bit time . table 23-3time segment syntax sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode will transfer a new value to the can bus at this point. sample point a node in receive mode will sample the bus at this point. if the three samples per bit option is selected then this point marks the position of the third sample. bit rate= no. of time quanta f tq sync _seg time segment 1 time seg. 2 1 4 ... 16 2 ... 8 8... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) memory map mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 281 23.11 memory map the mscan08 occupies 128 bytes in the cpu08 memory space. table 23-4. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchron. jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 $0500 control registers 9 bytes $0508 $0509 reserved 5 bytes $050d $050e error counters 2 bytes $050f $0510 identifier filter 8 bytes $0517 $0518 reserved 40 bytes $053f $0540 receive buffer $054f $0550 transmit buffer 0 $055f $0560 transmit buffer 1 $056f $0570 transmit buffer 2 $057f figure 23-9. mscan08 memory map mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 282 freescale semiconductor 23.12 programmer?s model of message storage this subsection details the organization of the re ceive and transmit message buffers and the associated control registers. for reasons of programmer interf ace simplification, the receive and transmit message buffers have the same outline. each message buffer al locates 16 bytes in the memory map containing a 13-byte data structure. an additional transmit buffer pr iority register (tbpr) is defined for the transmit buffers. 23.12.1 message buffer outline figure 23-11 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. the mapping of standard identifiers into the idr registers is shown in figure 23-12 . all bits of the 13-byte data structure are undefined out of reset. note the foreground receive buffer can be read anytime but cannot be written. the transmit buffers can be read or written anytime. 23.12.2 identifier registers the identifiers consist of either 11 bits (id10?id0) for the standard, or 29 bits (id28?id0) for the extended format. id10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. the priority of an identifier is defined to be highest for the smallest binary number. srr ? substitute remote request this fixed recessive bit is used only in extended forma t. it must be set to 1 by the user for transmission buffers and will be stored as received on the can bus for receive buffers. addr register name $05x0 identifier register 0 $05x1 identifier register 1 $05x2 identifier register 2 $05x3 identifier register 3 $05x4 data segment register 0 $05x5 data segment register 1 $05x6 data segment register 2 $05x7 data segment register 3 $05x8 data segment register 4 $05x9 data segment register 5 $05xa data segment register 6 $05xb data segment register 7 $05xc data length register $05xd transmit buffer priority register (1) $05xe unused $05xf unused 1. where x equals the following: x = 4 for receiver buffer x = 5 for transmit buffer 1 x = 6 for transmit buffer 2 x = 7 for transmit buffer 3 2. not applicable for receive buffers figure 23-10. message buffer organization programmer?s model of message storage mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 283 addr register bit 7 6 5 4 3 2 1 bit 0 $05b 0idr0 read: id28 id27 id26 id25 id24 id23 id22 id21 write: $05b 1idr1 read: id20 id19 id18 srr (=1) ide (=1) id17 id16 id15 write: $05b 2idr2 read: id14 id13 id12 id11 id10 id9 id8 id7 write: $05b 3idr3 read: id6 id5 id4 id3 id2 id1 id0 rtr write: $05b 4dsr0 read: db7db6db5db4db3db2db1db0 write: $05b 5dsr1 read: db7db6db5db4db3db2db1db0 write: $05b 6dsr2 read: db7db6db5db4db3db2db1db0 write: $05b 7dsr3 read: db7db6db5db4db3db2db1db0 write: $05b 8dsr4 read: db7db6db5db4db3db2db1db0 write: $05b 9dsr5 read: db7db6db5db4db3db2db1db0 write: $05b adsr6 read: db7db6db5db4db3db2db1db0 write: $05b bdsr7 read: db7db6db5db4db3db2db1db0 write: $05b cdlr read: dlc3 dlc2 dlc1 dlc0 write: = unimplemented figure 23-11. receive/transmit message buffer extended identifier (idrn) addrregister bit 7654321bit 0 $05b 0idr0 read: id10 id9 id8 id7 id6 id5 id4 id3 write: $05b 1idr1 read: id2 id1 id0 rtr ide(=0) write: $05b 2idr2 read: write: $05b 3idr3 read: write: = unimplemented figure 23-12. standard identifier mapping mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 284 freescale semiconductor ide ? id extended this flag indicates whether the extended or standard i dentifier format is applied in this buffer. in case of a receive buffer, the flag is set as being received and indicates to the cpu how to process the buffer identifier registers. in case of a transmit buffer, the flag indicates to the mscan08 what type of identifier to send. 1 = extended format, 29 bits 0 = standard format, 11 bits rtr ? remote transmission request this flag reflects the status of the remote transmission request bit in the can frame. in case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in case of a transmit buffer, this flag defines the setting of the rtr bit to be sent. 1 = remote frame 0 = data frame 23.12.3 data length register (dlr) this register keeps the data length field of the can frame. dlc3?dlc0 ? data length code bits the data length code contains the number of bytes (data byte count) of the respective message. at transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 23-5 shows the effect of setting the dlc bits. table 23-5. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008 programmer?s model of message storage mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 285 23.12.4 data segment registers (dsrn) the eight data segment registers contain the data to be transmitted or received. the number of bytes to be transmitted or being received is determined by the data length code in the corresponding dlr. 23.12.5 transmit buffer priority registers prio7?prio0 ? local priority this field defines the local priority of the associ ated message buffer. the local priority is used for the internal prioritisation process of the mscan08 an d is defined to be highest for the smallest binary number. the mscan08 implements the follow ing internal prioritisation mechanism: ? all transmission buffers with a cl eared txe flag participate in the prioritisation right before the sof is sent. ? the transmission buffer with the lowest loca l priority field wins the prioritisation. ? in case more than one buffer has the same lowest priority, the message buffer with the lower index number wins. address: $05bd bit 7654321bit 0 read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: reset: unaffected by reset figure 23-13. transmit buffer priority register (tbpr) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 286 freescale semiconductor 23.13 programmer?s mode l of control registers the programmer?s model has been laid out for maximum simplicity and efficiency. figure 23-14 gives an overview on the control register block of the mscan08. addr register bit 7 6 5 4 3 2 1 bit 0 $0500 cmcr0 read: 0 0 0 synch tlnken slpak slprq sftres write: $0501 cmcr1 read:00000 loopb wupm clksrc write: $0502 cbtr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0503 cbtr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0504 crflg read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: $0505 crier read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: $0506 ctflg read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: $0507 ctcr read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: $0508 cidac read: 0 0 idam1 idam0 0 0 idhit1 idhit0 write: $0509 reserved read: rrrrrrrr write: $050e crxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $050f ctxerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0510 cidar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0511 cidar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0512 cidar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0513 cidar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0514 cidmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0515 cidmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0516 cidmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0517 cidmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: = unimplemented r = reserved figure 23-14. mscan08 control register structure programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 287 23.13.1 mscan08 module control register 0 synch ? synchronized status this bit indicates whether the mscan08 is synchroni zed to the can bus and as such can participate in the communication process. 1 = mscan08 synchronized to the can bus 0 = mscan08 not synchronized to the can bus tlnken ? timer enable this flag is used to establish a link bet ween the mscan08 and the on-chip timer (see 23.9 timer link ). 1 = the mscan08 timer signal output is connected to the timer input. 0 = the port is connected to the timer input. slpak ? sleep mode acknowledge this flag indicates whether the mscan08 is in module internal sleep mode. it shall be used as a handshake for the sleep mode request (see 23.8.1 mscan08 sleep mode ). if the mscan08 detects bus activity while in sle ep mode, it clears the flag. 1 = sleep ? mscan08 in internal sleep mode 0 = wakeup ? mscan08 is not in sleep mode slprq ? sleep request, go to internal sleep mode this flag requests the mscan08 to go into an internal power-saving mode (see 23.8.1 mscan08 sleep mode ). 1 = sleep ? the mscan08 will go into internal sleep mode. 0 = wakeup ? the mscan08 will function normally. sftres ? soft reset when this bit is set by the cpu, the mscan08 immediately enters the soft reset state. any ongoing transmission or reception is aborted and synchronization to the bus is lost. the following registers enter and stay in their hard reset state: cmcr0, crflg, crier, ctflg, and ctcr. the registers cmcr1, cbtr0, cbtr1, cidac, cidar0?3, and cidmr0?3 can only be written by the cpu when the mscan08 is in soft reset state. the values of the error counters are not affected by soft reset. when this bit is cleared by the cpu, the mscan08 tries to synchronize to the can bus. if the mscan08 is not in bus-off state, it will be synchr onized after 11 recessive bits on the bus; if the mscan08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits. clearing sftres and writing to other bits in cmcr0 must be in separate instructions. 1 = mscan08 in soft reset state 0 = normal operation address: $0500 bit 7654321bit 0 read: 0 0 0 synch tlnken slpak slprq sftres write: reset:00000001 = unimplemented figure 23-15. module control register 0 (cmcr0) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 288 freescale semiconductor 23.13.2 mscan08 module control register 1 loopb ? loop back self-test mode when this bit is set, the mscan08 performs an in ternal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiv er internally. the rxcan input pin is ignored and the txcan output goes to the recessive state (logic ?1?). the mscan08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state the mscan08 ignores the bit sent during the ack slot of the can frame acknowledge field to insure proper reception of its own message. both transmit and receive interrupt are generated. 1 = activate loop back self-test mode 0 = normal operation wupm ? wakeup mode this flag defines whether the integrated low-pass filter is applied to protect the mscan08 from spurious wakeups (see 23.8.5 programmable wakeup function ). 1 = mscan08 will wake up the cpu only in case s of a dominant pulse on the bus which has a length of at least t wup . 0 = mscan08 will wake up the cpu after any recessive to dominant edge on the can bus. clksrc ? clock source this flag defines which clock source t he mscan08 module is driven from (see 23.10 clock system ). 1 = the mscan08 clock source is cgmout (see figure 23-7 ). 0 = the mscan08 clock source is cgmxclk/2 (see figure 23-7 ). note the cmcr1 register can be written only if the sftres bit in the mscan08 module control register is set address: $0501 bit 7654321bit 0 read:00000 loopb wupm clksrc write: reset:00000000 = unimplemented figure 23-16. module control register (cmcr1) programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 289 23.13.3 mscan08 bus timing register 0 sjw1 and sjw0 ? synchronization jump width the synchronization jump width (sjw) defi nes the maximum number of time quanta (t q ) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronizatio n on data transitions on the bus (see table 23-6 ). brp5?brp0 ? baud rate prescaler these bits determine the time quanta (t q ) clock, which is used to build up the individual bit timing, according to table 23-7 . note the cbtr0 register can be written onl y if the sftres bit in the mscan08 module control register is set. address: $0502 bit 7654321bit 0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: reset:00000000 figure 23-17. bus timing register 0 (cbtr0) table 23-6. synchronization jump width sjw1 sjw0 synchronization jump width 00 1 t q cycle 01 2 t q cycle 10 3 t q cycle 11 4 t q cycle table 23-7. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : :::::: : 111111 64 mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 290 freescale semiconductor 23.13.4 mscan08 bus timing register 1 samp ? sampling this bit determines the number of serial bus samples to be taken per bit time. if set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. for higher bit rates, samp should be cleared, which m eans that only one sample will be taken per bit. 1 = three samples per bit (1) 0 = one sample per bit tseg22?tseg10 ? time segment time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. time segment 1 (tseg1) and time segment 2 (tseg2) are programmable as shown in table 23-8 . the bit time is determined by the oscillator frequenc y, the baud rate prescaler, and the number of time quanta (t q ) clock cycles per bit as shown in table 23-8 ). note the cbtr1 register can only be writt en if the sftres bit in the mscan08 module control register is set. address: $0503 bit 7654321bit 0 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: reset:00000000 figure 23-18. bus timing register 1 (cbtr1) 1. in this case phase_seg1 mu st be at least 2 time quanta. table 23-8. time segment values tseg13 tseg12 tseg11 tseg10 time segment 1 tseg22 tseg21 tseg20 time segment 2 0 000 1 t q cycle (1) 1. this setting is not valid. please refer to table 23-4 for valid settings. 000 1 t q cycle (1) 0 001 2 t q cycles (1) 001 2 t q cycles 0 010 3t q cycles (1) ... . 0 011 4 t q cycles ... . . ... . 111 8t q cycles . ... . 1 111 16 t q cycles bit time= pres value f mscanclk ? number of time quanta programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 291 23.13.5 mscan08 r eceiver flag register (crflg) all bits of this register are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. a flag can be cleared only when the condition which caus ed the setting is valid no more. writing a 0 has no effect on the flag setting. every flag has an associated interrupt enable flag in the crier register. a hard or soft reset will clear the register. wupif ? wakeup interrupt flag if the mscan08 detects bus activity while in sleep mode, it sets the wupif flag. if not masked, a wake-up interrupt is pending while this flag is set. 1 = mscan08 has detected activity on the bus and requested wake-up. 0 = no wake-up interrupt has occurred. rwrnif ? receiver warning interrupt flag this flag is set when the mscan08 goes into warning status due to the receive error counter (rec) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set (1) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into receiver warning status. 0 = no receiver warning status has been reached. twrnif ? transmitter warning interrupt flag this flag is set when the mscan08 goes into warn ing status due to the transmit error counter (tec) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set (2) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into transmitter warning status. 0 = no transmitter warning status has been reached. rerrif ? receiver error passive interrupt flag this flag is set when the mscan08 goes into error passive status due to the receive error counter exceeding 127 and the bus-off interrupt flag is not set (3) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 has gone into receiver error passive status. 0 = no receiver error passive status has been reached. address: $0504 bit 7654321bit 0 read: wupif rwrnif twrnif rerrif terrif boffif ovrif rxf write: reset:00000000 figure 23-19. receiver flag register (crflg) 1. condition to set the flag: rwrnif = (96 rec) & rerrif & terrif & boffif 2. condition to set the flag: twrnif = (96 tec) & rerrif & terrif & boffif 3. condition to set the flag: rerrif = (127 rec 255) & boffif mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 292 freescale semiconductor terrif ? transmitter error passive interrupt flag this flag is set when the mscan08 goes into erro r passive status due to the transmit error counter exceeding 127 and the bus-off interrupt flag is not set (1) . if not masked, an error interrupt is pending while this flag is set. 1 = mscan08 went into transmit error passive status. 0 = no transmit error passive status has been reached. boffif ? bus-off interrupt flag this flag is set when the mscan08 goes into bu s-off status, due to the transmit error counter exceeding 255. it cannot be cleared before the mscan08 has monitored 128 times 11 consecutive ?recessive? bits on the bus. if not masked, an erro r interrupt is pending while this flag is set. 1 = mscan08has gone into bus-off status. 0 = no bus-off status has bee reached. ovrif ? overrun interrupt flag this flag is set when a data overrun condition occurs . if not masked, an error interrupt is pending while this flag is set. 1 = a data overrun has been detected since last clearing the flag. 0 = no data overrun has occurred. rxf ? receive buffer full the rxf flag is set by the mscan08 when a new me ssage is available in the foreground receive buffer. this flag indicates whether the buffer is loaded with a correctly received message. after the cpu has read that message from the receive buffer the rxf flag must be cleared to release the buffer. a set rxf flag prohibits the exchange of the background receive buffer into the foreground buffer. if not masked, a receive interrupt is pending while this flag is set. 1 = the receive buffer is full. a new message is available. 0 = the receive buffer is released (not full). note to ensure data integrity, no registers of the receive buffer shall be read while the rxf flag is cleared. note the crflg register is held in the reset state when the sftres bit in cmcr0 is set. 1. condition to set the flag: terrif = (128 tec 255) & boffif programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 293 23.13.6 mscan08 receiver inte rrupt enable register wupie ? wakeup interrupt enable 1 = a wakeup event will result in a wakeup interrupt. 0 = no interrupt will be generated from this event. rwrnie ? receiver warning interrupt enable 1 = a receiver warning status event will result in an error interrupt. 0 = no interrupt is generated from this event. twrnie ? transmitter warning interrupt enable 1 = a transmitter warning status event will result in an error interrupt. 0 = no interrupt is generated from this event. rerrie ? receiver error passive interrupt enable 1 = a receiver error passive status event will result in an error interrupt. 0 = no interrupt is generated from this event. terrie ? transmitter error passive interrupt enable 1 = a transmitter error passive status event will result in an error interrupt. 0 = no interrupt is generated from this event. boffie ? bus-off interrupt enable 1 = a bus-off event will result in an error interrupt. 0 = no interrupt is generated from this event. ovrie ? overrun interrupt enable 1 = an overrun event will result in an error interrupt. 0 = no interrupt is generated from this event. rxfie ? receiver full interrupt enable 1 = a receive buffer full (successful message reception) event will result in a receive interrupt. 0 = no interrupt will be generated from this event. note the crier register is held in the reset state when the sftres bit in cmcr0 is set. address: $0505 bit 7654321bit 0 read: wupie rwrnie twrnie rerrie terrie boffie ovrie rxfie write: reset:00000000 figure 23-20. receiver interrupt enable register (crier) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 294 freescale semiconductor 23.13.7 mscan08 transm itter flag register the abort acknowledge flags are read only. the trans mitter buffer empty flags are read and clear only. a flag can be cleared by writing a 1 to the corresponding bit position. writing a 0 has no effect on the flag setting. the transmitter buffer empty flags each hav e an associated interrupt enable bit in the ctcr register. a hard or soft reset will resets the register. abtak2?abtak0 ? abort acknowledge this flag acknowledges that a message has been aborted due to a pending abort request from the cpu. after a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the messag e has been aborted successfully or has been sent. the abtakx flag is cleared implicitly whenev er the corresponding txe flag is cleared. 1 = the message has been aborted. 0 = the message has not been aborted, thus has been sent out. txe2?txe0 ? transmitter empty this flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. the cpu must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. the mscan08 sets the flag after the message has been sent successfully. the flag is also set by the mscan08 when the transmission request was successfully aborted due to a pending abort request (see 23.12.5 transmit buffer priority registers ). if not masked, a receive interrupt is pending while this flag is set. clearing a txex flag also clears the correspon ding abtakx flag (abtak, see above). when a txex flag is set, the correspondi ng abtrqx bit (abtrq, see 23.13.8 mscan08 transmitter control register ) is cleared. 1 = the associated message buffer is empty (not scheduled). 0 = the associated message buffer is full (loaded with a message due for transmission). note to ensure data integrity, no registers of the transmit buffers should be written to while the associated txe flag is cleared. note the ctflg register is held in the reset state when the sftres bit in cmcr0 is set. address: $0506 5 bit 7654321bit 0 read: 0 abtak2 abtak1 abtak0 0 txe2 txe1 txe0 write: reset:00000111 = unimplemented figure 23-21. transmitter flag register (ctflg) programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 295 23.13.8 mscan08 transmitter control register abtrq2?abtrq0 ? abort request the cpu sets an abtrqx bit to request that an already scheduled message buffer (txe = 0) be aborted. the mscan08 will grant the request if th e message has not already started transmission, or if the transmission is not successful (lost ar bitration or error). when a message is aborted the associated txe and the abort acknowledge flag (abtak) (see 23.13.7 mscan08 transmitter flag register ) will be set and an txe interrupt is generated if enabled. the cpu cannot reset abtrqx. abtrqx is cleared implicitly whenever the associated txe flag is set. 1 = abort request pending 0 = no abort request note the software must not clear one or more of the txe flags in ctflg and simultaneously set the respective abtrq bit(s). txeie2?txeie0 ? transmitter empty interrupt enable 1 = a transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = no interrupt is generated from this event. note the ctcr register is held in the reset state when the sftres bit in cmcr0 is set. address: $0507 bit 7654321bit 0 read: 0 abtrq2 abtrq1 abtrq0 0 txeie2 txeie1 txeie0 write: reset:00000000 = unimplemented figure 23-22. transmitter control register (ctcr) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 296 freescale semiconductor 23.13.9 mscan08 identifier acceptance control register idam1?idam0? identifier acceptance mode the cpu sets these flags to define the i dentifier acceptance filter organization (see 23.5 identifier acceptance filter ). table 23-9 summarizes the different settings. in ?filter closed? mode no messages will be accepted so that the foreground buffer will never be reloaded. idhit1?idhit0? identifier acceptance hit indicator the mscan08 sets these flags to indicate an identifier acceptance hit (see 23.5 identifier acceptance filter ). table 23-9 summarizes the different settings. the idhit indicators are always related to the message in the foreground buffer. when a message gets copied from the background to the foregrou nd buffer, the indicators are updated as well. note the cidac register can be written only if the sftres bit in the cmcr0 is set. address: $0508 bit 7654321bit 0 read: 0 0 idam1 idam0 0 0 idhit1 idhit0 write: reset:00000000 = unimplemented figure 23-23. identifier accepta nce control register (cidac) table 23-9. identifier acceptance mode settings idam1 idam0 identifier acceptance mode 0 0 single 32-bit acceptance filter 0 1 two 16-bit acceptance filter 1 0 four 8-bit acceptance filters 1 1 filter closed table 23-10. identifier acceptance hit indication idhit1 idhit0 identi fier acceptance hit 0 0 filter 0 hit 0 1 filter 1 hit 1 0 filter 2 hit 1 1 filter 3 hit programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 297 23.13.10 mscan08 recei ve error counter this register reflects the status of the mscan 08 receive error counter. the register is read only. 23.13.11 mscan08 transm it error counter this register reflects the status of the mscan08 transmit error counter. the register is read only. note both error counters may only be read when in sleep or soft reset mode. address: $050e bit 7654321bit 0 read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: reset:00000000 = unimplemented figure 23-24. receiver error counter (crxerr) address: $050f bit 7654321bit 0 read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: reset:00000000 = unimplemented figure 23-25. transmit error counter (ctxerr) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 298 freescale semiconductor 23.13.12 mscan08 identifier a cceptance registers on reception each message is written into the back ground receive buffer. the cpu is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). the acceptance registers of the mscan08 are applied on the idr0 to idr3 registers of incoming messages in a bit by bit manner. for extended identifiers, all four acceptance and mask registers are applied. for standard identifiers only the first two (cidmr0/1 and cidar0/1) are applied. ac7?ac0 ? acceptance code bits ac7?ac0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identifier mask register. note the cidar0?3 registers can be writt en only if the sftres bit in cmcr0 is set cidar0 address: $0510 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar1 address: $050511 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar2 address: $0512 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset cidar3 address: $0513 bit 7654321bit 0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: reset: unaffected by reset figure 23-26. identifier acceptance registers (cidar0?cidar3) programmer?s model of control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 299 23.13.13 mscan08 iden tifier mask registers (cidmr0-3) the identifier mask registers specify which of the co rresponding bits in the identif ier acceptance register are relevant for acceptance filtering. for standard identif iers it is required to program the last three bits (am2-am0) in the mask register cidmr1 to ?don?t care?. am7?am0 ? acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifi er bit before a match will be detected. the message will be accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not af fect whether or not the message is accepted. 1 = ignore corresponding acceptance code register bit. 0 = match corresponding acceptance code register and identifier bits. note the cidmr0-3 registers can be written only if the sftres bit in the cmcr0 is set cidmro address: $0514 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr1 address: $0515 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr2 address: $0516 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset cidmr3 address: $0517 bit 7654321bit 0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: reset: unaffected by reset figure 23-27. identifier mask registers (cidmr0?cidmr3) mscan controller (mscan08) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 300 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 301 chapter 24 keyboard module (kbi) 24.1 introduction the keyboard interrupt module (kbd) provides five independently maskable external interrupt pins. this module is onl y available on 64-pin package options. 24.2 features kbd features include: ? five keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask ? hysteresis buffers ? programmable edge-only or edge- and level- interrupt sensitivity ? automatic interrupt acknowledge ? exit from low-power modes 24.3 functional description writing to the kbie4?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port g or port h pin as a keyboard in terrupt pin. enabling a ke yboard interrupt pin also enables its internal pullup device. a low level applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. ? if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. ? if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 302 freescale semiconductor keyboard module (kbi) figure 24-1. keyboard module block diagram register name bit 7654321bit 0 keyboard status and control register (kbscr) read:0000keyf0 imaskk modek write: ackk reset:00000000 keyboard interrupt enable register (kbier) read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 24-2. i/o register summary table 24-1. i/o register address summary register kbscr kbier address $001b $0021 kb0ie kb4ie . . . keyboard interrupt dq ck clr v dd modek imaskk keyboard interrupt ff request vector fetch decoder ackk internal bus reset to pullup enable kbd4 kbd0 to pullup enable synchronizer keyf keyboard initialization mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 303 if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the in terrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the kbi vector address. ? return of all enabled keyboard interrupt pins to a high level. as long as any enabled keyboard interrupt pin is low, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays low. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 24.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bi t in the keyboard status and control register 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. keyboard module (kbi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 304 freescale semiconductor another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddrg bits in data direction register g. 2. configure the keyboard pins as outputs by se tting the appropriate ddrh bits in data direction register h. 3. write logic 1s to the appropriate port g and port h data register bits. 4. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 24.5 low-power modes the wait and stop instructions put the mcu in low-power-consumption standby modes. 24.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 24.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 24.6 keyboard module during break interrupts the bcfe bit in the break flag control register (bfc r) enables software to clear status bits during the break state. see chapter 13 break module (brk) . to allow software to clear the keyf bit during a brea k interrupt, write a logic 1 to the bcfe bit. if keyf is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the keyf bit during the break state, write a lo gic 0 to the bcfe bit. with bcfe at logic 0, writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. see 24.7.1 keyboard status and control register . 24.7 i/o registers the following registers control and monitor operation of the keyboard module: ? keyboard status and control register (kbscr) ? keyboard interrupt enable register (kbier) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 305 24.7.1 keyboard stat us and control register the keyboard status and control register: ? flags keyboard interrupt requests ? acknowledges keyboard interrupt requests ? masks keyboard interrupt requests ? controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as logic 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001b bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 24-3. keyboard status and control register (kbscr) keyboard module (kbi) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 306 freescale semiconductor 24.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or dis ables each port g and each port h pin to operate as a keyboard interrupt pin. kbie4?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = pdx pin enabled as keyboard interrupt pin 0 = pdx pin not enabled as keyboard interrupt pin address: $0021 bit 7654321bit 0 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 24-4. keyboard interrupt enable register (kbier) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 307 chapter 25 timer interface module a (tima) 25.1 introduction this section describes the timer interface module (tim a). the tima is a 6-channel timer that provides a timing reference with input capture, output compare and pulse-width-modulation functions. figure 25-1 is a block diagram of the tima. for further information regarding timers on m68h c08 family devices, pleas e consult the hc08 timer reference manual, tim08rm/ad. 25.2 features features of the tima include: ? six input capture/output compare channels ? rising-edge, falling-edge or any-edge input capture trigger ? set, clear or toggle output compare action ? buffered and unbuffered pulse widt h modulation (pwm) signal generation ? programmable tima clock input ? 7 frequency internal bus clock prescaler selection ? external tima clock input (4 mhz maximum frequency) ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tima counter stop and reset bits timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 308 freescale semiconductor figure 25-1. tima block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte2 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock ptd6/atd14/taclk pte2/tach0 pte3/tach1 ptf0/tach2 ptf1/tach3 logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte3 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h:tch2l ms2a els2b els2a ptf0 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h:tch3l ms3a els3b els3a ptf1 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic 16-bit comparator 16-bit latch tch4h:tch4l ms4a els4b els4a ptf2 channel 4 tov4 ch4ie ch4f ch5max ms4b logic inter- rupt logic 16-bit comparator 16-bit latch tch5h:tch5l ms5a els5b els5a ptf3 channel 5 tov5 ch5ie ch5f ch5max logic inter- rupt logic ptf2/tach4 ptf3/tach5 functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 309 25.3 functional description figure 25-1 shows the tima structure. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-counter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh?tamodl, control the modulo value of the tima counter. software can read the tima counter value at any time without affecting the counting sequence. the six tima channels are programmable independently as input capture or output compare channels. addr. register name bit 7654321bit 0 $0020 tima status/control register (tasc) tof toie tstop trst 0 ps2 ps1 ps0 $0021 reservedrrrrrrrr $0022 tima counter register high (tacnth) bit 15 14 13 12 11 10 9 bit 8 $0023 tima counter register low (tacntl)bit 7654321bit 0 $0024 tima counter modulo reg. high (tamodh) bit 15 14 13 12 11 10 9 bit 8 $0025tima counter modulo reg. low (tamodl)bit 7654321bit 0 $0026 tima ch. 0 status/control register (tasc0) ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max $0027 tima ch. 0 register high (tach0h) bit 15 14 13 12 11 10 9 bit 8 $0028 tima ch. 0 register low (tach0l)bit 7654321bit 0 $0029 tima ch. 1 status/control register (tasc1) ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max $002a tima ch. 1 register high (tach1h) bit 15 14 13 12 11 10 9 bit 8 $002b tima ch. 1 register low (tach1l)bit 7654321bit 0 $002c tima ch. 2 status/control register (tasc2) ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max $002d tima ch. 2 register high (tach2h) bit 15 14 13 12 11 10 9 bit 8 $002e tima ch. 2 register low (tach2l)bit 7654321bit 0 $002f tima ch. 3 status/control register (tasc3) ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max $0030 tima ch. 3 register high (tach3h) bit 15 14 13 12 11 10 9 bit 8 $0031 tima ch. 3 register low (tach3l)bit 7654321bit 0 $0032 tima ch. 4 status/control register (tasc4) ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max $0033 tima ch. 4 register high (tach4h) bit 15 14 13 12 11 10 9 bit 8 $0034 tima ch. 4 register low (tach4l)bit 7654321bit 0 $0035 tima ch. 5 status/control register (tasc5) ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max $0036 tima ch. 5 register high (tach5h) bit 15 14 13 12 11 10 9 bit 8 $0037 tima ch. 5 register low (tach5l)bit 7654321bit 0 r = reserved figure 25-2. tima i/o register summary timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 310 freescale semiconductor 25.3.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, ptd6/atd14/taclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tima status and control register select the tima clock source. 25.3.2 input capture an input capture function has three basic parts: ed ge select logic, an input capture latch and a 16-bit counter. two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the correspondi ng input capture edge detector senses a defined transition. the polarity of the active edge is programma ble. the level transition which triggers the counter transfer is defined by the corresponding input ed ge bits (elsxb and elsxa in tasc0 through tasc5 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channel, the tima latches the contents of the tima counter into the tima channel registers, tachxh?tachxl. input captures can generate tima cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture in terrupts or by polling the status flag bit. the free-running counter contents are transferred to the tima channel register (tachxh?tachxl see 25.8.5 tima channel registers ) on each proper signal transition regar dless of whether the tima channel flag (ch0f?ch5f in tasc0?tasc5 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register 2 bus cy cles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a perio d, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establis h a time reference. in this case, an input capture function is used in conjuncti on with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 25.8.5 tima channel registers ). because both input captures and output compares are refer enced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the tima channel register (tachxh?tachxl). 25.3.3 output compare with the output compare function, the tima can gener ate a periodic pulse with a programmable polarity, duration and frequency. when the counter reaches the value in the registers of an output compare channel, the tima can set, clear or toggle the chan nel pin. output compares can generate tima cpu interrupt requests. functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 311 25.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 25.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tima over flow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tima may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current counter overflow period. writing a larg er value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 25.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 registers initially controls the output on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (0 or 1) that control the output are the ones written to last. tasc0 controls and monitors the buffered output compare function and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3 /tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately control the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the output compare value in the tima channel 2 registers initially controls the output on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (2 or 3) that control the output are the ones written to last. tasc2 controls and monitors the buffered output compare function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1 /tach3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the ptf2 pin. the tima channel registers of the linked pair alternately control the output. setting the ms4b bit in tima channel 4 status and control register (tasc4) links channel 4 and channel 5. the output compare value in the tima channel 4 registers initially controls the output on the timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 312 freescale semiconductor ptf2 pin. writing to the tima channel 5 registers enables the tima channel 5 registers to synchronously control the output after the tima overflows. at eac h subsequent overflow, the tima channel registers (4 or 5) that control the output are the ones written to last. tasc4 controls and monitors the buffered output compare function and tima channel 5 status and contro l register (tasc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 25.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between overflows is the period of the pwm signal. as figure 25-3 shows, the output compare value in the tima channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tima to clear the channel pin on output compare if the polar ity of the pwm pulse is 1. program the tima to set the pin if the polarity of the pwm pulse is 0. figure 25-3. pwm period and pulse width the value in the tima counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tima counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 25.8.1 tima status and control register ). the value in the tima channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 incremen ts. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50%. ptex/tchx period pulse width overflow overflow overflow output compare output compare output compare functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 313 25.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 25.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the tima channel registers. an unsynchronized write to the tima channel regi sters to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tima overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tima may pass the new value before it is written to the tima channel registers. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable ti ma overflow interrupts and write the new value in the tima overflow interrupt routine. the tima ov erflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 25.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2/tach0 pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tima channel 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially cont rol the pulse width on the pte2/tach0 pin. writing to the tima channel 1 registers enables the tima cha nnel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pulse width are the ones wri tten to last. tasc0 controls and monitors the buffered pwm function and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the li nked pair alternately control the pulse width of the output. setting the ms2b bit in tima channel 2 status and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially contro l the pulse width on the ptf0/tach2 pin. writing to the tima channel 3 registers enables the tima cha nnel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 314 freescale semiconductor (2 or 3) that control the pulse width are the ones wri tten to last. tasc2 controls and monitors the buffered pwm function and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. channels 4 and 5 can be linked to form a buffered pwm channel whose output appears on the ptf2 pin. the tima channel registers of the linked pair al ternately control the pulse width of the output. setting the ms4b bit in tima channel 4 status and control register (tasc4) links channel 4 and channel 5. the tima channel 4 registers initially control the pulse width on the ptf2 pin. writing to the tima channel 5 registers enables the tima channel 5 r egisters to synchronously control the pulse width at the beginning of the next pwm period. at each subs equent overflow, the tima channel registers (4 or 5) that control the pulse width are the ones written to last. tasc4 controls and monitors the buffered pwm function and tima channel 5 status and control regi ster (tasc5) is unused. while the ms4b bit is set, the channel 5 pin, ptf3, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 25.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by setting the tima stop bit, tstop. b. reset the tima counter and prescaler by setting the tima reset bit, trst. 2. in the tima counter modulo registers (tamo dh?tamodl) write the value for the required pwm period. 3. in the tima channel x registers (tachxh?tachxl) write the value for the required pulse width. 4. in tima channel x status and control register (tascx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa (see table 25-2 ). b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level (see table 25-2 ). note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima status control register (tasc) clear the tima stop bit, tstop. interrupts mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 315 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tima channel 0 registers (tach0h?tach0l) initially control the buffered pwm output. tima status control register 0 (tasc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tima channel 2 registers (tach2h?tach2l) initially control the buffered pwm output. tima status control register 2 (tasc2) controls and monitors the pwm si gnal from the linked channels. ms2b takes priority over ms2a. setting ms4b links channels 4 and 5 and configures them for buffered pwm operation. the tima channel 4 registers (tach4h?tach4l) initially control the buffered pwm output. tima status control register 4 (tasc4) controls and monitors the pwm si gnal from the linked channels. ms4b takes priority over ms4a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output (see 25.8.4 tima channel status and control registers ). 25.4 interrupts the following tima sources c an generate interrupt requests: ? tima overflow flag (tof) ? the tof bit is se t when the tima counter reaches the modulo value programmed in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. to f and toie are in the tima status and control register. ? tima channel flags (ch5f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tima cpu inte rrupt requests are controlled by the channel x interrupt enable bit, chxie. 25.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 25.5.1 wait mode the tima remains active after the execution of a wait instruction. in wait mode, the tima registers are not accessible by the cpu. any enabled cpu interrupt request from the tima can bring the mcu out of wait mode. if tima functions are not required during wait mode , reduce power consumption by stopping the tima before executing the wait instruction. 25.5.2 stop mode the tima is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tima counter. tima operation resumes when the mcu exits stop mode. timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 316 freescale semiconductor 25.6 tima during break interrupts a break interrupt stops the tima c ounter and inhibits input captures. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state (see 9.7.3 sim break flag control register ). to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 25.7 i/o signals port d shares one of its pins with the tima. port e s hares two of its pins with the tima and port f shares four of its pins with the tima. ptd6/atd14/taclk is an external clock input to the tima prescaler. the six tima channel i/o pins are pte2/tach0, pte3/tach1, ptf0/tach2, ptf1/tach3, ptf2, and ptf3. 25.7.1 tima clock pin (ptd6/atd14/ taclk) ptd6/atd14/taclk is an external clock input that can be the clock source for the tima counter instead of the prescaled internal bus cl ock. select the ptd6/atd14/taclk input by writing logic 1s to the three prescaler select bits, ps[2:0] (see 25.8.1 tima status and control register ). the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is the least: 4 mhz or bus frequency 2. ptd6/atd14/taclk is available as a general-pur pose i/o pin or adc channel when not used as the tima clock input. when the ptd6/atd14/taclk pin is the tima clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 25.7.2 tima channel i/ o pins (ptf3?ptf0/tach2 and pte3/tach1?pte2/tach0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. pte2/tach0, ptf0/tach2 and ptf2 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------- ------------------ t su + i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 317 25.8 i/o registers these i/o registers control and monitor tima operation: ? tima status and control register (tasc) ? tima control registers (tacnth?tacntl) ? tima counter modulo registers (tamodh?tamodl) ? tima channel status and control registers (tasc 0, tasc1, tasc2, tasc3, tasc4 and tasc5) ? tima channel registers (tach0h?tach0l, tach1h?tach1l, tach2h?tach2l, tach3h?tach3l, tach4h?tach4l and tach5h?tach5l) 25.8.1 tima status and control register the tima status and control register: ? enables tima overflow interrupts ? flags tima overflows ? stops the tima counter ? resets the tima counter ? prescales the tima counter clock tof ? tima overflow flag bit this read/write flag is set when the tima counter reaches the modulo value programmed in the tima counter modulo registers. clear tof by reading t he tima status and control register when tof is set and then writing a logic 0 to tof. if another tima overflow occurs befor e the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a logic 1 to tof has no effect. 1 = tima counter has reached modulo value. 0 = tima counter has not reached modulo value. toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ? tima stop bit this read/write bit stops the tima counter. countin g resumes when tstop is cleared. reset sets the tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 25-4. tima status and control register (tasc) timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 318 freescale semiconductor note do not set the tstop bit before entering wait mode if the tima is required to exit wait mode. also, when the tstop bit is set and input capture mode is enabled, input captures are inhibited until tstop is cleared. when using the tstop to stop the timer counter, see if any timer flags are set. if a timer flag is set, it must be cleared by clearing the tstop, then clearing the flag, then setting the tstop again. trst ? tima reset bit setting this write-only bit resets the tima counter and the tima prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tima counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the ptd6/atd 14/taclk pin or one of the seven prescaler outputs as the input to the tima counter as table 25-1 shows. reset clears the ps[2:0] bits. 25.8.2 tima c ounter registers the two read-only tima counter registers contain the high and low bytes of the value in the tima counter. reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears the tima counter registers. note if tacnth is read during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. table 25-1. prescaler selection ps[2:0] tima clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 ptd6/atd14/taclk i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 319 25.8.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the modulo value, the overflow flag (tof) becomes set and the tima counter resumes counting from $0000 at the next timer clock. writing to the high byte (tamodh) inhibits the tof bit and overflow inte rrupts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note reset the tima counter before writing to the tima counter modulo registers. register name and address tacnth ? $0022 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 register name and address tacntl ? $0023 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 25-5. tima counter registers (tacnth and tacntl) register name and address tamodh ? $0024 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address tamodl ? $0025 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 figure 25-6. tima counter modulo registers (tamodh and tamodl) timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 320 freescale semiconductor 25.8.4 tima channel stat us and control registers each of the tima channel status and control registers: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare or pwm operation ? selects high, low or toggling output on output compare ? selects rising edge, falling edge or any e dge as the active input capture trigger ? selects output toggling on tima overflow ? selects 0% and 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation register name and address tasc0 ? $0026 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address tasc1 ? $0029 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved register name and address tasc2 ? $002c bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 register name and address tasc3 ? $002f bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset:00000000 register name and address tasc4 ? $0032 bit 7654321bit 0 read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 reset:00000000 figure 25-7. tima channel status and control registers (tasc0?tasc5) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 321 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tima counter registers matches the value in the tima channel x registers. when chxie = 1, clear chxf by reading tima channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tima channel 0, tima channel 2 and tima channel 4 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tach1 pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tach3 pin to general-purpose i/o. setting ms4b disables the channel 5 status and control register and reverts tach5 pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 25-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation register name and address tasc5 ? $0035 bit 7654321bit 0 read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 r reset:00000000 r = reserved figure 25-7. tima channel status and control registers (tasc0?tasc5) (continued) timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 322 freescale semiconductor when elsxb:a = 00, this read/write bit selects the initial output level of the tachx pin once pwm, output compare mode or input capture mode is enabled. see table 25-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tima status and control register (tasc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e or port f and pin ptex/tachx or pin ptfx/tachx is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes trans parent to the respective pin when pwm, input capture mode or output compare operation mode is enabled. table 25-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note before enabling a tima channel register for input capture operation, make sure that the ptex/tachx pin or ptfx /tachx pin is stable for at least two bus clocks. table 25-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 323 tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggle on tima counter overflow. note when tovx is set, a tima counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 25-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 25-8. chxmax latency 25.8.5 tima c hannel registers these read/write registers contain the captured tima counter value of the input capture function or the output compare value of the output compare function. the state of the tima channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0) reading the high byte of the tima channel x registers (tachxh) inhibits input captures un til the low byte (tachxl) is read. in output compare mode (msxb?msxa 0:0) writing to the high byte of the tima channel x registers (tachxh) inhibits output compares and the chxf bit until the low byte (tachxl) is written. register name and address tach0h ? $0027 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset figure 25-9. tima channel registers (tach0h/l?tach5h/l) (sheet 1 of 3) output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 324 freescale semiconductor register name and address tach0l ? $0028 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tach1h ? $002a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach1l ? $002b bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tach2h ? $002d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach2l ? $002e bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tach3h ? $0030 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach3l ? $0031 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 25-9. tima channel registers (tach0h/l?tach5h/l) (sheet 2 of 3) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 325 register name and address tach4h ? $0033 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach4l ? $0034 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset register name and address tach5h ? $0036 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address tach5l ? $0037 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 25-9. tima channel registers (tach0h/l?tach5h/l) (sheet 3 of 3) timer interface module a (tima) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 326 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 327 chapter 26 analog-to-digital converter (adc) 26.1 introduction this section describes the analog-to-digital converte r (adc-15). the adc is an 8-bit analog-to-digital converter. for further information regarding analog-to-digital converters on freescale microcontrollers, please consult the hc08 adc re ference manual, adcrm/ad. 26.2 features features of the adc module include: ? 15 channels with multiplexed input ? linear successive approximation ? 8-bit resolution ? single or continuous conversion ? conversion complete flag or conversion complete interrupt ? selectable adc clock 26.3 functional description fifteen adc channels are available for sa mpling external sources at pins ptd6/atd14/taclk ? ptd0/atd8 and ptb7/atd7 ? ptb0/atd0. an analog multiplexer allows the single adc converter to select one of 15 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation registe r-based counters. when the c onversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 26-1 . analog-to-digital converter (adc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 328 freescale semiconductor figure 26-1. adc block diagram 26.3.1 adc port i/o pins ptd6/atd14/taclk ? ptd0/atd8 and ptb7/atd7 ? ptb0/atd0 are general-purpose i/o pins that share with the adc channels. the channel select bits define which adc channel/p ort pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as in put to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. note do not use adc channels atd14 or atd12 when using the ptd6/atd14/taclk or ptd4/atd12/tbclk pins as the clock inputs for the 16-bit timers. internal data bus read ddrb/ddrb write ddrb/ddrd reset write ptb/ptd read ptb/ptd ptbx/ptdx ddrbx/ddrdx ptbx/ptdx interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock cgmxclk bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x interrupts mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 329 26.3.2 voltage conversion when the input voltage to the adc equals v refh (see 28.1.6 adc characteristics ), the adc converts the signal to $ff (full scale). if the input voltage equals v ssa, the adc converts it to $00. input voltages between v refh and v ssa are a straight-line linear conversion. conversion accuracy of all other input voltages is not guaranteed. avoid current injection on unused adc inputs to prevent potential conversion error. note input voltage should not exceed the analog supply voltages. 26.3.3 conversion time conversion starts after a write to the adscr (adc status control register, $0038), and requires between 16 and 17 adc clock cycles to complete. conversion time in terms of the number of bus cycles is a function of adiclk select, cgmxclk frequency, bus frequency, and adiv prescaler bits. for example, with a cgmxclk frequency of 4 mhz, bus frequency of 8 mhz, and fixed adc clock frequency of 1 mhz, one conversion will take between 16 and 17 s and there will be between 128 bus cycles between each conversion. sample rate is approximately 60 khz. refer to 28.1.6 adc characteristics . 26.3.4 continuous conversion in the continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit (adc status control register, $0038) is cleared. the coco bit is set after the first conversion and will stay set for the next several conversions until the next write of the adc status and control register or the next read of the adc data register. 26.3.5 accuracy and precision the conversion process is monotoni c and has no missing codes. see 28.1.6 adc characteristics for accuracy information. 26.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit (adc status control register, $0038) is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 16 to 17 adc clock cycles conversion time = ???????????? adc clock frequency number of bus cycles = conversion time x bus frequency analog-to-digital converter (adc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 330 freescale semiconductor 26.5 low-power modes the following subsections des cribe the low-power modes. 26.5.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register before executing the wait instruction. 26.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 26.6 i/o signals the adc module has 15 channels that are shared with i/o ports b and d. refer to 28.1.6 adc characteristics for voltages referenced below. 26.6.1 adc analog power pin (v ddaref )/adc voltage reference pin (v refh ) the adc analog portion uses v ddaref as its power pin. connect the v dda /v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddaref for good results. v refh is the high reference voltage for all analog-to-digital conversions. note route v ddaref carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. v ddaref must be present for operation of the adc. 26.6.2 adc analog ground pin (v ssa )/adc voltage refe rence low pin (v refl ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . v refl is the lower reference supply for the adc. 26.6.3 adc volt age in (adcvin) adcvin is the input voltage signal from one of the 15 adc channels to the adc module. 26.7 i/o registers these i/o registers control and monitor adc operation: ? adc status and control register (adscr) ? adc data register (adr) ? adc clock register (adiclk) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 331 26.7.1 adc status and control register the following paragraphs describe the functi on of the adc status and control register. coco ? conversions complete bit when the aien bit is a logic 0, the coco is a r ead-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. if the aien bit is a logic 1, the coco is a read/w rite bit which selects the cpu to service the adc interrupt request. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conver sion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bi t field which is used to select one of 15 adc channels. channel selection is detailed in the followin g table. care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. see table 26-1 . the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when th e adc is not used. reset sets these bits. note recovery from the disabled state requi res one conversion cycle to stabilize. address: $0038 bit 7654321bit 0 read: coco aien adco ch4 ch3 ch2 ch1 ch0 write: r reset:00011111 r= reserved figure 26-2. adc status and control register (adscr) analog-to-digital converter (adc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 332 freescale semiconductor 26.7.2 adc data register one 8-bit result register is provided. this regi ster is updated each time an adc conversion completes. table 26-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptd0/atd8/atd8 01001 ptd1/atd9/atd9 01010ptd2/atd10/atd10 01011ptd3/atd11/atd11 0 1 1 0 0 ptd4/atd12/tbclk/atd12 01101ptd5/atd13/atd13 0 1 1 1 0 ptd6/atd14/taclk/atd14 range 01111 ($0f) to 11010 ($1a) unused (see note 1) unused (see note 1) 11011 reserved 1 1 1 0 0 unused (see note 1) 11101 v refh (see note 2) 11110 v ssa /v refl (see note 2) 11111 [adc power off] notes: 1. if any unused channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal re ference nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applica- tions. address: $0039 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 26-3. adc data register (adr) i/o registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 333 26.7.3 adc input clock register this register selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field which se lects the divide ratio used by the adc to generate the internal adc clock. table 26-2 shows the available clock confi gurations. the adc clock should be set to approximately 1 mhz. adiclk ? adc input clock register bit adiclk selects either bus clock or cgmxclk as t he input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for the adc. if cgmxclk is less t han 1 mhz, use the pll-generated bus clock as the clock source. as long as the internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. see 28.1.6 adc characteristics . 1 = internal bus clock 0 = external clock (cgmxclk) note during the conversion process, changi ng the adc clock will result in an incorrect conversion. address: $003a bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset: 0 0000000 = unimplemented figure 26-4. adc input clock register (adiclk) table 26-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock /1 0 0 1 adc input clock / 2 0 1 0 adc input clock / 4 0 1 1 adc input clock / 8 1 x x adc input clock / 16 x = don?t care f xclk or bus frequency 1 mhz = ??????????? adiv[2:0] analog-to-digital converter (adc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 334 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 335 chapter 27 byte data link controller (bdlc) 27.1 introduction the byte data link controller (bdlc) provides access to an external serial communication multiplex bus, operating according to the society of au tomotive engineers ( sae) j1850 protocol. the bdlc-d is only available on the mc68hc908as60a. 27.2 features features of the bdlc module include: ? sae j1850 class b data communications network in terface compatible and is o compatible for low speed (< 125 kbps) serial data communications in automotive applications ? 10.4 kbps variable pulse width (vpw) bit format ? digital noise filter ? collision detection ? hardware cyclical redundancy chec k (crc) generation and checking ? two power-saving modes with autom atic wakeup on network activity ? polling and cpu interrupts available ? block mode receive and transmit supported ? supports 4x receive mode, 41.6 kbps ? digital loopback mode ? analog loopback mode ? in-frame response (ifr) types 0, 1, 2, and 3 supported 27.3 functional description figure 27-1 shows the organization of the bdlc module. the cpu interface contains the software addressable registers and provides the link between the cpu and the buffers. the buffers provide storage for data received and data to be transmitted onto the j1850 bus. the protocol handler is responsible for the encoding and decoding of data bits and special message symbols during trans mission and reception. the mux interface provides the link between the bdlc digital section and the analog physical interface. the wave shaping, driving, and digitizing of data is performed by the physical interface. use of the bdlc module in mess age networking fully implements the sae standard j1850 class b data communication network interface specification. note it is recommended that the reader be familiar with the sae j1850 document and iso serial communication docum ent prior to proceeding with this chapter of the specification. byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 336 freescale semiconductor figure 27-1. bdlc block diagram addr. name bit 7 6 5 4 3 2 1 bit 0 $003b bdlc analog and rou5ndtrip delay register (bard) read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r $003c bdlc control register 1 (bcr1) read: imsg clks r1 r0 00 ie wcm write: r r $003d bdlc control register 2 (bcr2) read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: $003e bdlc state vector register (bsvr) read: 0 0 i3 i2 i1 i0 0 0 write:rrr r rrrr $003f bdlc data register (bdr) read: bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 write: r = reserved figure 27-2. bdlc i/o register summary cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc functional description mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 337 27.3.1 bdlc operating modes the bdlc has five main modes of operation which interact with the power supplies, pins, and the remainder of the mcu as shown in figure 27-3 . figure 27-3. bdlc operating modes state diagram 27.3.1.1 power off mode this mode is entered from reset mode whenever the bdlc supply voltage, v dd , drops below its minimum specified value for the bdlc to guarantee operati on. the bdlc will be placed in reset mode by low-voltage reset (lvr) before being powered down. in th is mode, the pin input and output specifications are not guaranteed. 27.3.1.2 reset mode this mode is entered from the power off mode whenever the bdlc supply voltage, v dd , rises above its minimum specified value (v dd ?10%) and some mcu reset source is asserted. the internal mcu reset must be asserted while powering up the bdlc or an unknown state will be entered and correct operation cannot be guaranteed. reset mode is also entered from any other mode as soon as one of the mcu?s possible reset sources (such as lvr, por, cop watchdog, and reset pin, etc.) is asserted. in reset mode, the internal bdlc voltage references are operative; v dd is supplied to the internal circuits which are held in their reset state; and the internal bd lc system clock is runni ng. registers will assume their reset condition. outputs are held in their pr ogrammed reset state. therefore, inputs and network activity are ignored. v dd > v dd (minimum) and power off reset bdlc stop run v dd v dd (minimum) stop instruction or (from any mode) bdlc wait network activity or wait instruction and wcm = 1 wait instruction and wcm = 0 any mcu reset source asserted no mcu reset source asserted any mcu reset source asserted network activity or other mcu wakeup other mcu wakeup cop, illaddr, pu, reset, lvr, por byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 338 freescale semiconductor 27.3.1.3 run mode this mode is entered from the reset mode after al l mcu reset sources are no longer asserted. run mode is entered from the bdlc wait mode whenever activity is sensed on the j1850 bus. run mode is entered from the bdlc stop mode whenever network activity is sensed, although messages will not be received properly until the clocks ha ve stabilized and the cpu is in run mode also. in this mode, normal network operation takes place. the user should ensure that all bdlc transmissions have ceased before exiting this mode. 27.3.1.4 bdlc wait mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a wait instruction and if the wcm bit in the bcr1 register is cleared previously. in this mode, the bdlc internal clocks continue to run. the first passive-to-ac tive transition of the bus generates a cpu interrupt request from the bdlc which wakes up the bdlc and the cpu. in addition, if the bdlc receives a valid eof symbol while oper ating in wait mode, then the bdlc also will generate a cpu interrupt request which wakes up the bdlc and the cpu. see 27.7.1 wait mode . 27.3.1.5 bdlc stop mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait inst ruction and the wcm bit in the bcr1 register is set previously. in this mode, the bdlc internal clocks are stopped but the physical interface circuitry is placed in a low-power mode and awaits network activity. if network activity is sensed, then a cpu interrupt request will be generated, restarting the bdlc internal clocks. see 27.7.2 stop mode . 27.3.1.6 digital loopback mode when a bus fault has been detected, the digital loopbac k mode is used to determine if the fault condition is caused by failure in the node?s internal circuits or elsewhere in the network, including the node?s analog physical interface. in this mode, the transmit digita l output pin (bdtxd) and the receive digital input pin (bdrxd) of the digital interface are disconnected from the analog physical interface and tied together to allow the digital portion of the bdlc to transmit and receive its own messages without driving the j1850 bus. 27.3.1.7 analog loopback mode analog loopback is used to determine if a bus fault has been caused by a failure in the node?s off-chip analog transceiver or elsewhere in the network. the bcld analog loopback m ode does not modify the digital transmit or receive functions of the bd lc. it does, however, ensure that once analog loopback mode is exited, the bdlc will wait for an idle bus condition before participation in network communication resumes. if the off-chip analog transceiver has a loo pback mode, it usually causes the input to the output drive stage to be looped back into the receiver, allowing the node to receive messages it has transmitted without driving the j1850 bus. in this mode, the output to the j1850 bus is typi cally high impedance. this allows the communication path through the analog trans ceiver to be tested without interfering with network activity. using the bdlc analog loopback mode in conjunction with the analog transceiver?s loopback mode ensures that, once the off-chip anal og transceiver has exited loopback mode, the bcld will not begin communicating before a kn own condition exists on the j1850 bus. bdlc mux interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 339 27.4 bdlc mux interface the mux interface is responsible for bit encoding/dec oding and digital noise filtering between the protocol handler and the physical interface. figure 27-4. bdlc block diagram 27.4.1 rx digital filter the receiver section of the bdlc includes a digital lo w pass filter to remove narrow noise pulses from the incoming message. an outline of the digital filter is shown in figure 27-5 . figure 27-5. bdlc rx digital filter block diagram 27.4.1.1 operation the clock for the digital filter is provided by the mux interface clock (see f bdlc parameter in table 27-3 ). at each positive edge of the clock signal, the current state of the receiver physical interface (bdrxd) signal is sampled. the bdrxd signal state is used to determine whether the counter should increment or decrement at the next negat ive edge of the clock signal. cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc 4-bit up/down couter data latch up/down out d q filtered rx data out mux interface input sync dq rx data from physical interface clock (bdrxd) byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 340 freescale semiconductor the counter will increment if the input data sample is high but decrement if the input sample is low. therefore, the counter will thus progress either up toward 15 if, on average, the bdrxd signal remains high or progress down toward 0 if, on average, the bdrxd signal remains low. when the counter eventually reaches the value 15, the digital filter decides that the condition of the bdrxd signal is at a stable logic level 1 and the data latch is set, causing the filtered rx data signal to become a logic level 1. furthermore, the counter is prevented from overflowing and can only be decremented from this state. alternatively, should the counter even tually reach the value 0, the digita l filter decides that the condition of the bdrxd signal is at a stable logic level 0 and t he data latch is reset, causing the filtered rx data signal to become a logic level 0. furthermore, t he counter is prevented from underflowing and can only be incremented from this state. the data latch will retain its value until the count er next reaches the opposite end point, signifying a definite transition of the signal. 27.4.1.2 performance the performance of the digital filter is best descri bed in the time domain rather than the frequency domain. if the signal on the bdrxd signal transitions, then there will be a delay before that transition appears at the filtered rx data output signal. this delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling point s. this filter delay must be taken into account when performing message arbitration. for example, if the frequency of the mux interface clock (f bdlc ) is 1.0486 mhz, then the period (t bdlc ) is 954 ns and the maximum filter delay in the absence of noise will be 15.259 s. the effect of random noise on the bdrxd signal depends on the characteristics of the noise itself. narrow noise pulses on the bdrxd signal will be ignored comple tely if they are shorter than the filter delay. this provides a degree of low pass filtering. if noise occurs during a symbol transition, the dete ction of that transition can be delayed by an amount equal to the length of the noise burst. this is just a reflection of the uncertainty of where the transition is truly occurring within the noise. noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length, will be detected by the next stage of th e bdlc?s receiver as an invalid symbol. noise pulses that are longer than the shortest allo wable symbol length will be detected normally as an invalid symbol or as invalid dat a when the frame?s crc is checked. 27.4.2 j1850 frame format all messages transmitted on the j1850 bus are structured using the format shown in . j1850 states that each message has a maximum length of 101 pwm bit times or 12 vpw bytes, excluding sof, eod, nb, and eof, with each byte transmitted msb first. all vpw symbol lengths in the following descriptions are typical values at a 10.4 kbps bit rate. bdlc mux interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 341 sof ? start-of-frame symbol all messages transmitted onto the j1850 bus must begin with a long-active 200- s period sof symbol. this indicates the start of a new message transmi ssion. the sof symbol is not used in the crc calculation. data ? in-message data bytes the data bytes contained in the message include the message priority/type, message id byte (typically the physical address of the responder), and any ac tual data being transmitted to the receiving node. the message format used by the bdlc is similar to the 3-byte consolidated header message format outlined by the sae j1850 document. see sae j1850 ? class b data communications network interface for more information about 1- and 3-byte headers. messages transmitted by the bdlc onto the j1850 bus must contain at least one data byte and, therefore, can be as short as one data byte and on e crc byte. each data byte in the message is eight bits in length and is transmitted msb to lsb. crc ? cyclical redundancy check byte this byte is used by the receiver(s) of each mess age to determine if any errors have occurred during the transmission of the message. the bdlc calculates the crc byte and appends it onto any messages transmitted onto the j 1850 bus. it also performs crc detection on any messages it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 + x 4 + x 3 + x 2 + 1. the remainder polynomial initially is set to all ones. each byte in the message after t he start of frame (sof) symbol is processed serially through the crc generation circuitry. the one?s complement of the remainder then becomes the 8-bit crc byte, which is appended to the message after the data bytes in msb-to-lsb order. when receiving a message, the bdlc uses the same di visor polynomial. all data bytes, excluding the sof and end of data symbols (eod) but including the crc byte, are used to check the crc. if the message is error free, the remainder polynomial will equal x 7 + x 6 + x 2 = $c4, regardless of the data contained in the message. if the calculated crc does not equal $c4, the bdlc will recognize this as a crc error and set the crc error flag in the bsvr. eod ? end-of-data symbol the eod symbol is a long 200- s passive period on the j1850 bus used to signify to any recipients of a message that the transmission by the originator has completed. no flag is set upon reception of the eod symbol. data e o d optional i f s idle sof priority (data0) message id (data1) data n crc n b ifr eof idle . j1850 bus message format (vpw) byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 342 freescale semiconductor ifr ? in-frame response bytes the ifr section of the j1850 message format is optiona l. users desiring further definition of in-frame response should review the sae j1850 ? class b data communi cations networ k interface specification. eof ? end-of-frame symbol this symbol is a long 280- s passive period on the j1850 bus and is longer than an end-of-data (eod) symbol, which signifies the end of a message. since an eof symbol is longer than a 200- s eod symbol, if no response is transmitted after an eo d symbol, it becomes an eof, and the message is assumed to be completed. the eof flag is set upon receiving the eof symbol. ifs ? inter-frame separation symbol the ifs symbol is a 20- s passive period on the j1850 bus which allows proper synchronization between nodes during continuous message transmiss ion. the ifs symbol is transmitted by a node after the completion of the end-of-frame (eof) period and, therefore, is seen as a 300- s passive period. when the last byte of a message has been transmitt ed onto the j1850 bus and the eof symbol time has expired, all nodes then must wait for the ifs symbol time to expire before transmitting a start-of-frame (sof) symbol, marking the beginning of another message. however, if the bdlc is waiting for the ifs peri od to expire before beginning a transmission and a rising edge is detected before the ifs time has expired, it will synchronize internally to that edge. if a write to the bdr register (for instance, to initiate transmission) occurred on or before 104 ? t bdlc from the received rising edge, then the bdlc will transmit and arbitrate for the bus. if a cpu write to the bdr register occurred after 104 ? t bdlc from the detection of the rising edge, then the bdlc will not transmit, but will wait for the ne xt ifs period to expire before attempting to transmit the byte. a rising edge may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the comp letion of the ifs period at different times. to allow for individual clock tolerances, receivers mu st synchronize to any sof occurring during an ifs period. note if two messages are received with a 300 s ( 1 s ) interframe separation (ifs) as measured at the rx pin, the start-of-frame (sof) symbol of the second message will generate an invalid symbol interrupt. this interrupt results in the second message being lost and will therefore be unavailable to the application software. implement ations of this bdlc design on silicon have not been exposed to interframe separation rates faster than 320 s in practical application and have therefore previously not exhibited this behavior. ensuring that no nodes on the j1850 network transmit messages at 300 s ( 1 s ) ifs will avoid this missed message frame. in addition, developing application software to robustly handle lost messages will minimize application impact. break ? break the bdlc cannot transmit a break symbol. if the bdlc is transmitting at the time a break is detected, it treats the break as if a transmission error had occurred and halts transmission. bdlc mux interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 343 if the bdlc detects a break symbol while receivi ng a message, it treats the break as a reception error and sets the invalid symbol flag in the bsvr, also ignoring the frame it was receiving. if while receiving a message in 4x mode, the bdlc de tects a break symbol, it treats the break as a reception error, sets the invalid symbol flag, and exits 4x mode (for example, the rx4xe bit in bcr2 is cleared automatically). if bus control is requir ed after the break symbol is received and the ifs time has elapsed, the programmer must resend t he transmission byte using highest priority. note the j1850 protocol break symbol is not related to the hc08 break module. chapter 13 break module (brk) idle ? idle bus an idle condition exists on the bus during any passi ve period after expiration of the ifs period (for instance, 300 s). any node sensing an idle bus conditi on can begin transmission immediately. 27.4.3 j1850 vpw symbols huntsinger?s variable pulse width modulation (vpw) is an encoding technique in which each bit is defined by the time between successive tr ansitions and by the level of the bus between transitions (for instance, active or passive). active and passive bits are used alternately. this encoding technique is used to reduce the number of bus transitions for a given bit rate. each logic 1 or logic 0 contains a si ngle transition and can be at either the active or passive level and one of two lengths, either 64 s or 128 s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the start-of-frame (sof), end-of-data (eod), end-of-frame (eof), and inter-frame separation (ifs) symbols always will be encoded at an assigned level and length. see figure 27-6 . each message will begin with an sof symbol an active symbol and, therefore, each data byte (including the crc byte) will begin with a passive bit, regar dless of whether it is a logic 1 or a logic 0. all vpw bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate. logic 0 a logic 0 is defined as either: ? an active-to-passive transition followed by a passive period 64 s in length, or ? a passive-to-active transition followed by an active period 128 s in length see figure 27-6. j1850 vpw symbols with nominal symbol times (a) . logic 1 a logic 1 is defined as either: ? an active-to-passive transition followed by a passive period 128 s in length, or ? a passive-to-active transition followed by an active period 64 s in length see figure 27-6. j1850 vpw symbols with nominal symbol times (b ). normalization bit (nb) the nb symbol has the same property as a logic 1 or a logic 0. it is only used in ifr message responses. break signal (break) the break signal is defined as a pa ssive-to-active transition followed by an active period of at least 240 s (see figure 27-6. j1850 vpw symbols wi th nominal symbol times (c) ). byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 344 freescale semiconductor figure 27-6. j1850 vpw symbols with nominal symbol times start-of-frame symbol (sof) the sof symbol is defined as passive-to-active transition followed by an active period 200 s in length (see figure 27-6. j1850 vpw symbols with nominal symbol times (d )). this allows the data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0. end-of-data symbol (eod) the eod symbol is defined as an active-to-passive transition followed by a passive period 200 s in length (see figure 27-6. j1850 vpw symbols with nominal symbol times (e) ). end-of-frame symbol (eof) the eof symbol is defined as an active-to-pa ssive transition followed by a passive period 280 s in length (see figure 27-6. j1850 vpw symbols with nominal symbol times (f) ). if no ifr byte is transmitted after an eod symbol is transmitted, after another 80 s the eod becomes an eof, indicating completion of the message. inter-frame separation symbol (ifs) the ifs symbol is defined as a passive period 300 s in length. the 20- s ifs symbol contains no transition, since when used it always appends to an eof symbol (see figure 27-6. j1850 vpw symbols with nominal symbol times (g) ). 128 s active passive 64 s or (a) logic 0 128 s active passive 64 s or ( b) logic 1 200 s active passive ( d) start of frame active passive (f) end of frame 240 s (c) break 200 s ( e) end of data 280 s (g) inter-frame 20 s 300 s idle > 300 s (h) idle separation bdlc mux interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 345 idle an idle is defined as a passive period greater than 300 s in length. 27.4.4 j1850 vpw valid/inval id bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus have been defined to allow for variations in oscillator frequencies. in many case s the maximum time allowed to define a data bit or symbol is equal to the minimum time allo wed to define another data bit or symbol. since the minimum resolution of the bdlc for deter mining what symbol is bei ng received is equal to a single period of the mux interface clock (t bdlc ), an apparent separation in these maximum time/minimum time concurrences equal to one cycle of t bdlc occurs. this one clock resolution allows the bdlc to different iate properly between the different bits and symbols. this is done without reducing the valid window for rece iving bits and symbols fr om transmitters onto the j1850 bus which have varying oscillator frequencies. in huntsinger?s? variable pulse widt h (vpw) modulation bit encoding, the tolerances for both the passive and active data bits received and the symbols receiv ed are defined with no gaps between definitions. for example, the maximum length of a passive logic 0 is equal to the minimum lengt h of a passive logic 1, and the maximum length of an active logic 0 is equa l to the minimum length of a valid sof symbol. invalid passive bit see figure 27-7 (1) . if the passive-to-active received transition beginning the next data bit or symbol occurs between the active-to-passive transiti on beginning the current data bit (or symbol) and a , the current bit would be invalid. figure 27-7. j1850 vpw received passive symbol times a bc b a (1) invalid passive bit (2) valid passive logic 0 (3) valid passive logic 1 64 s 128 s cd (4) valid eod symbol 200 s active passive active passive active passive active passive byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 346 freescale semiconductor valid passive logic 0 see figure 27-7 (2) . if the passive-to-active received transiti on beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 0. valid passive logic 1 see figure 27-7 (3) . if the passive-to-active received transiti on beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 1. valid eod symbol see figure 27-7 (4) . if the passive-to-active received transiti on beginning the next data bit (or symbol) occurs between c and d , the current symbol would be considered a valid end-of-data symbol (eod). figure 27-8. j1850 vpw received passive eof and ifs symbol times valid eof and ifs symbol in figure 27-8 (1) , if the passive-to-active received transit ion beginning the sof symbol of the next message occurs between a and b , the current symbol will be considered a valid end-of-frame (eof) symbol. see figure 27-8 (2) . if the passive-to-active received transit ion beginning the sof symbol of the next message occurs between c and d, the current symbol will be considered a valid eof symbol followed by a valid inter-frame separation sy mbol (ifs). all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, d ue to variations in clock frequencies and bus loading, some nodes may recognize a valid if s symbol before others and immediately begin transmitting. therefore, any time a node waiting to transmit detects a passive -to-active transition once a valid eof has been detected, it should immediat ely begin transmission, initiating the arbitration process. idle bus in figure 27-8 (2) , if the passive-to-active received transition beginning the start-of-frame (sof) symbol of the next message does not occur before d, the bus is considered to be idle, and any node wishing to transmit a message may do so immediately. invalid active bit in figure 27-9 (1) , if the active-to-passive received transitio n beginning the next data bit (or symbol) occurs between the passive-to-active transiti on beginning the current data bit (or symbol) and a , the current bit would be invalid. cd (2) valid eof+ 280 s 300 s a b ( 1) valid eof symbol active passive active passive ifs symbol bdlc mux interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 347 figure 27-9. j1850 vpw received active symbol times valid active logic 1 in figure 27-9 (2) , if the active-to-passive received transitio n beginning the next data bit (or symbol) occurs between a and b , the current bit would be considered a logic 1. valid active logic 0 in figure 27-9 (3) , if the active-to-passive received transitio n beginning the next data bit (or symbol) occurs between b and c , the current bit would be considered a logic 0. valid sof symbol in figure 27-9 (4) , if the active-to-passive received transitio n beginning the next data bit (or symbol) occurs between c and d , the current symbol would be c onsidered a valid sof symbol. valid break symbol in figure 27-10 , if the next active-to-passive received transition does not occur until after e , the current symbol will be considered a valid break sym bol. a break symbol s hould be followed by a start-of-frame (sof) symbol beginning the next message to be transmitted onto the j1850 bus. see j1850 frame format for bdlc response to break symbols. a bc b a (1) invalid active bit (2) valid active logic 1 (3) valid active logic 0 64 s 128 s cd (4) valid sof symbol 200 s active passive active passive active passive active passive byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 348 freescale semiconductor figure 27-10. j1850 vpw received break symbol times 27.4.5 message arbitration message arbitration on the j1850 bus is accompli shed in a non-destructive manner, allowing the message with the highest priority to be transmitted, wh ile any transmitters which lose arbitration simply stop transmitting and wait for an idle bus to begin transmitting again. if the bdlc wants to transmit onto the j1850 bus, but detects that another message is in progress, it waits until the bus is idle. however, if multiple nodes beg in to transmit in the same synchronization window, message arbitration will occur beginning with the first bit after the sof sym bol and will continue with each bit thereafter. the variable pulse width modulation (vpw) symbols and j1850 bus electrical characteristics are chosen carefully so that a logic 0 (active or passive type) wi ll always dominate over a logic 1 (active or passive type) that is simultaneously transmi tted. hence, logic 0s are said to be dominant and logic 1s are said to be recessive. whenever a node detects a dominant bit on bdrxd w hen it transmitted a recessive bit, the node loses arbitration and immediately stops transmitti ng. this is known as bitwise arbitration. figure 27-11. j1850 vpw bitwise arbitrations (2) valid break symbol 240 s e active passive transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 0 transmitter a detects an active state on the bus and stops transmitting transmitter b wins passive active passive active passive active 0 0 1 1 1 data bit 2 1 1 1 data bit 3 0 0 0 0 1 arbitration and continues transmitting bdlc protocol handler mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 349 since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and will always win arbitrati on. for instance, a message with priority 000 will win arbitration over a message with priority 011. this method of arbitration will work no matter how m any bits of priority encoding are contained in the message. during arbitration, or even throughout the transmi tting message, when an opposite bit is detected, transmission is stopped immediately unless it occurs on the 8th bit of a byte. in this case, the bdlc automatically will append up to two extra logic 1 bits and then stop transmitting. these two extra bits will be arbitrated normally and thus will not interfere wi th another message. the second logic 1 bit will not be sent if the first loses arbitration. if the bdlc has lost arbitration to another valid message, then the two extra logic 1s will not corrupt the current message. howe ver, if the bdlc has lost arbitration due to noise on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored as a noise-corrupted message. 27.5 bdlc protocol handler the protocol handler is responsib le for framing, arbitration, crc generation/checking, and error detection. the protocol handler conforms to sae j1850 ? class b data communications network interface . note freescale assumes that the reader is familiar with the j1850 specification before this protocol handler description is read. figure 27-12. bdlc block diagram cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 350 freescale semiconductor 27.5.1 protocol architecture the protocol handler contains the state machine, rx shadow register, tx shadow register, rx shift register, tx shift register, and loopback multiplexer as shown in figure 27-13 . figure 27-13. bdlc protocol handler outline 27.5.2 rx and tx shift registers the rx shift register gathers received serial data bits from the j1850 bus and makes them available in parallel form to the rx shadow register. the tx shift register takes data, in parallel form, from the tx shadow register and presents it serially to the state machine so that it can be transmitted onto the j1850 bus. 27.5.3 rx and tx shadow registers immediately after the rx shift register has completed shifting in a byte of data, this data is transferred to the rx shadow register and rdrf or rxifr is set (see 27.6.4 bdlc state vector register ) and an interrupt is generated if the interrupt enable bit (ie) in bcr1 is set. after the transfer takes place, this new data byte in the rx shadow register is available to t he cpu interface, and the rx shift register is ready to shift in the next byte of data. data in the rx shadow register must be retrieved by the cpu before it is overwritten by new data from the rx shift register. rx shift register to cpu interface and rx/tx buffers state machine to physical interface rx data tx data control 8 tx shift register bdtxd rxd control 8 rx shadow register tx shadow register loopback bdrxd bdtxd multiplexer dloop from bcr2 aloop loopback control bdlc protocol handler mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 351 once the tx shift register has completed its shifting o peration for the current byte, the data byte in the tx shadow register is loaded into the tx shift register. a fter this transfer takes place, the tx shadow register is ready to accept new data from the cpu when tdre flag in bsvr is set. 27.5.4 digital loopback multiplexer the digital loopback multiplexer connec ts rxd to either bdtxd or bdrxd, depending on the state of the dloop bit in the bcr2 register (see 27.6.3 bdlc control register 2 ). 27.5.5 state machine all of the functions associated with performing t he protocol are executed or controlled by the state machine. the state machine is responsible fo r framing, collision detec tion, arbitration, crc generation/checking, and error detection. the followi ng sections describe the bdlc ?s actions in a variety of situations. 27.5.5.1 4x mode the bdlc can exist on the same j1850 bus as modul es which use a special 4x (41.6 kbps) mode of j1850 variable pulse width modulation (vpw) operation. the bdlc cannot transmit in 4x mode, but can receive messages in 4x mode, if the rx4x bit is set in bcr2 register. if the rx4x bit is not set in the bcr2 register, any 4x message on the j1850 bus is treated as noise by the bdlc and is ignored. 27.5.5.2 receiving a message in block mode although not a part of the sae j1850 protocol, the bdlc does allow for a specia l block mode of operation of the receiver. as far as the bdlc is concern ed, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all of the other features of the frame remain the same, including the sof, crc, and eod symbols. another node wishing to send a block mode transmissi on must first inform all other nodes on the network that this is about to happen. this is usually ac complished by sending a special predefined message. 27.5.5.3 transmitting a message in block mode a block mode message is transmitted inherently by si mply loading the bytes one by one into the bdr register until the message is complete. the programmer should wait until the tdre flag (see 27.6.4 bdlc state vector register ) is set prior to writing a new byte of data into the bdr register. the bdlc does not contain any predefined maximum j1850 message length requirement. 27.5.5.4 j1850 bus errors the bdlc detects several types of transmit and rece ive errors which can occur during the transmission of a message onto the j1850 bus. transmission error if the message transmitted by the bdlc contains invalid bits or framing symbols on non-byte boundaries, this constitutes a transmission error. when a transmission error is detected, the bdlc immediately will cease transmitting. the error conditi on ($1c) is reflected in the bsvr register (see table 27-5 ). if the interrupt enable bit (ie in bcr1) is set, a cpu interrupt request from the bdlc is generated. byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 352 freescale semiconductor crc error a cyclical redundancy check (crc) error is detected when the data bytes and crc byte of a received message are processed and the crc calculation result is not equal to $c4. the crc code will detect any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. the crc error flag ($18 in bsvr) is set when a crc error is detected. (see 27.6.4 bdlc state vector register .) symbol error a symbol error is detected when an abnormal (invalid ) symbol is detected in a message being received from the j1850 bus. however, if the bdlc is transmi tting when this happens, it will be treated as a loss of arbitration ($14 in bsvr) rather than a transmitter error. the ($1c) symbol invalid or the out-of-range flag is set when a symbol error is detect ed. therefore, ($1c) symbol invalid flag is stacked behind the ($14) loa flag during a transmission error process. (see 27.6.4 bdlc state vector register .) framing error a framing error is detected if an eod or eof symbol is detected on a non-byte boundary from the j1850 bus. a framing error also is detected if the bdlc is transmitting the eod and instead receives an active symbol. the ($1c) sym bol invalid or the out-of-range flag is set when a framing error is detected. (see 27.6.4 bdlc state vector register .) bus fault if a bus fault occurs, the response of the bdlc will depend upon the type of bus fault. if the bus is shorted to battery, the bdlc will wait for the bus to fall to a passive state before it will attempt to transmit a message. as long as the short remains, the bdlc will never attempt to transmit a message onto the j1850 bus. if the bus is shorted to ground, the bdlc will se e an idle bus, begin to transmit the message, and then detect a transmission error ($1c in bsvr), since t he short to ground would not allow the bus to be driven to the active (dominant) sof state. the bdlc will abort that transmission and wait for the next cpu command to transmit. in any case, if the bus fault is temporary, as soon as the fault is cleared, the bdlc will resume normal operation. if the bus fault is permanent, it may resu lt in permanent loss of communication on the j1850 bus. (see bdlc state vector register.) break ? break if a break symbol is received while the bdlc is transmitting or receiving, an invalid symbol ($1c in bsvr) interrupt will be generated. r eading the bsvr register (see 27.6.4 bdlc state vector register .) will clear this interrupt condition. the bdlc will wait for the bus to idle, then wait for a start-of-frame (sof) symbol. the bdlc cannot transmit a br eak symbol. it can only receive a br eak symbol from the j1850 bus. bdlc cpu interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 353 27.5.5.5 summary 27.6 bdlc cpu interface the cpu interface provides the interface between the cpu and the bdlc and consists of five user registers. ? bdlc analog and roundtrip delay register (bard) ? bdlc control register 1 (bcr1) ? bdlc control register 2 (bcr2) ? bdlc state vector register (bsvr) ? bdlc data register (bdr) figure 27-14. bdlc block diagram table 27-1. bdlc j1850 bus error summary error condition bdlc function transmission error for invalid bits or framing symbols on non-byte boundaries, invalid symbol interrupt will be generated. bdlc stops transmission. cyclical redundancy check (crc) error crc error interrupt will be generated. the bdlc will wait for sof. invalid symbol: bdlc receives invalid bits (noise) the bdlc will abort transmission immediately. invalid symbol interrupt will be generated. framing error invalid symbol interrupt will be generated. the bdlc will wait for start-of-frame (sof). bus short to v dd the bdlc will not transmit until the bus is idle. bus short to gnd thermal overload will shut down physical interface. fault condition is reflected in bsvr as an invalid symbol. bdlc receives break symbol. the bdlc will wait for the next valid sof. invalid symbol interrupt will be generated. cpu interface to j1850 bus mux interface protocol handler physical interface to cpu bdlc byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 354 freescale semiconductor 27.6.1 bdlc analog and roundtrip delay register this register programs the bdlc to compensate for vari ous delays of different external transceivers. the default delay value is16 s. timing adjustments from 9 s to 24 s in steps of 1 s are available. the bard register can be written only once after each re set, after which they become read-only bits. the register may be read at any time. ate ? analog transceiver enable bit the analog transceiver enable (ate) bit is used to se lect either the on-board or an off-chip analog transceiver. 1 = select on-board analog transceiver 0 = select off-chip analog transceiver note this device does not contain an on-board transceiver. this bit should be programmed to a 0 for proper operation. rxpol ? receive pin polarity bit the receive pin polarity (rxpol) bit is used to select the polarity of an incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding it back to the digital receive pin. 1 = select normal/true polarity; true non-inverted signal from the j1850 bus; for example, the external transceiver does not invert the receive signal 0 = select inverted polarity, where an external tr ansceiver inverts the receive signal from the j1850 bus b03?b00 ? bard offset bits table 27-2 shows the expected transceiver delay with respect to bard offset values. address: $003b bit 7654321bit 0 read: ate rxpol 00 bo3 bo2 bo1 bo0 write: r r reset:11000111 r= reserved figure 27-15. bdlc analog and roundtrip delay register (bard) table 27-2. bdlc transceiver delay bard offset bits b0[3:0] corresponding expected transceiver?s delays ( s) 0000 9 0001 10 0010 11 0011 12 0100 13 0101 14 0110 15 0111 16 bdlc cpu interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 355 27.6.2 bdlc cont rol register 1 this register is used to configure and control the bdlc. imsg ? ignore message bit this bit is used to disable the receiver unt il a new start-of-frame (sof) is detected. 1 = disable receiver. when set, all bdlc interrupt requests will be masked and the status bits will be held in their reset state. if this bit is set while the bdlc is receiving a message, the rest of the incoming message will be ignored. 0 = enable receiver. this bit is cleared automatically by the rec eption of an sof symbol or a break symbol. it will then generate interrupt requests and will allow changes of the status register to occur. however, these interrupts may still be masked by the interrupt enable (ie) bit. clks ? clock bit the nominal bdlc operating frequency (f bdlc ) must always be 1.048576 mhz or 1 mhz for j1850 bus communications to take place. the clks register bit allows the user to select the frequency (1.048576 mhz or 1 mhz) used to adjust symbol timing automatically. 1 = binary frequency (1.048576 mhz) selected for f bdlc 0 = integer frequency (1 mhz) selected for f bdlc r1 and r0 ? rate select bits these bits determine the amount by which the frequency of the mcu cgmxclk signal is divided to form the mux interface clock (f bdlc ) which defines the basic timing resolution of the mux interface. they may be written only once after reset, after which they become read-only bits. the nominal frequency of f bdlc must always be 1.048576 mhz or 1.0 mhz for j1850 bus communications to take place. hence, the val ue programmed into these bits is dependent on the chosen mcu system clock frequency per table 27-3 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 24 address: $003c bit 7654321bit 0 read: imsg clks r1 r0 00 ie wcm write: r r reset:11100000 r= reserved figure 27-16. bdlc control register 1 (bcr1) table 27-2. bdlc transceiver delay (continued) bard offset bits b0[3:0] corresponding expected transceiver?s delays ( s) byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 356 freescale semiconductor . ie? interrupt enable bit this bit determines whether the bdlc will generate cpu interrupt requests in run mode. it does not affect cpu interrupt requests when exiting the bdlc stop or bdlc wait modes. interrupt requests will be maintained until all of the interrupt request sour ces are cleared by performing the specified actions upon the bdlc?s registers. interrupts that were pending at the time that this bit is cleared may be lost. 1 = enable interrupt requests from bdlc 0 = disable interrupt requests from bdlc if the programmer does not wish to use the interrupt capability of the bdlc, the bdlc state vector register (bsvr) can be polled periodically by t he programmer to determine bdlc states. see 27.6.4 bdlc state vector register for a description of the bsvr. wcm ? wait clock mode bit this bit determines the operation of the bdlc during cpu wait mode. see stop mode and wait mode for more details on its use. 1 = stop bdlc internal cl ocks during cpu wait mode 0 = run bdlc internal clocks during cpu wait mode 27.6.3 bdlc cont rol register 2 this register controls transmitter operations of the bdlc. it is recommended that bset and bclr instructions be used to manipulate data in this register to ensure that the register?s content does not change inadvertently. aloop ? analog loopback mode bit this bit determines whether the j1850 bus will be dr iven by the analog physical interface?s final drive stage. the programmer can use this bit to reset th e bdlc state machine to a known state after the off-chip analog transceiver is placed in loopback mode. when the user clears aloop, to indicate that table 27-3. bdlc rate selection f xclk frequency r1 r0 division f bdlc 1.049 mhz 0 0 1 1.049 mhz 2.097 mhz 0 1 2 1.049 mhz 4.194 mhz 1 0 4 1.049 mhz 8.389 mhz 1 1 8 1.049 mhz 1.000 mhz 0 0 1 1.00 mhz 2.000 mhz 0 1 2 1.00 mhz 4.000 mhz 1 0 4 1.00 mhz 8.000 mhz 1 1 8 1.00 mhz address: $003d bit 7654321bit 0 read: aloop dloop rx4xe nbfs teod tsifr tmifr1 tmifr0 write: reset:11000000 figure 27-17. bdlc control register 2 (bcr2) bdlc cpu interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 357 the off-chip analog transceiver is no longer in loopback mode, the bdlc waits for an eof symbol before attempting to transmit. 1 = input to the analog physical interface?s final drive stage is looped back to the bdlc receiver. the j1850 bus is not driven. 0 = the j1850 bus will be driven by the bdlc. after the bit is cleared, the bdlc requires the bus to be idle for a minimum of end-of-frame symbol time (t trv4 ) before message reception or a minimum of inter-frame symbol time (t trv6 ) before message transmission. (see 28.1.15 bdlc transmitter vpw symbol timings . dloop ? digital loopback mode bit this bit determines the source to which the digital receive input (bdrxd) is connected and can be used to isolate bus fault conditions (see figure 27-13 ). if a fault condition has been detected on the bus, this control bit allows the programmer to connect the digita l transmit output to the digital receive input. in this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. if no faults exist in the bdlc, the fault is in the phy sical interface block or elsewhere on the j1850 bus. 1 = when set, bdrxd is connected to bdtxd. the bdlc is now in digital loopback mode. 0 = when cleared, bdtxd is not connected to bdrxd. the bdlc is taken out of digital loopback mode and can now drive the j1850 bus normally. rx4xe ? receive 4x enable bit this bit determines if the bdlc operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. this feature is useful for fast download of data into a j1850 node for diagnostic or factory programming of the node. 1 = when set, the bdlc is put in 4x receive-only operation. 0 = when cleared, the bdlc transmits and receives at 10.4 kbps. nbfs ? normalization bit format select bit this bit controls the format of the normalization bit (nb). (see figure 27-18 .) sae j1850 strongly encourages using an active long (logic 0) for in-f rame responses containing cyclical redundancy check (crc) and an active short (logic 1) for in-frame responses without crc. 1 = nb that is received or transmitted is a 0 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 1 when the response part of an in-frame response (ifr) does not end with a crc byte. 0 = nb that is received or transmitted is a 1 wh en the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a 0 when the response part of an in-frame response (ifr) does not end with a crc byte. teod ? transmit end of data bit this bit is set by the programmer to indicate the end of a message is being sent by the bdlc. it will append an 8-bit crc after completing transmission of the current byte. this bit also is used to end an in-frame response (ifr). if the transmit shadow regi ster is full when teod is set, the crc byte will be transmitted after the current byte in the tx shift register and the byte in the tx shadow register have been transmitted. (see 27.5.3 rx and tx shadow registers for a description of the transmit shadow register.) once teod is set, the transmit data register empty flag (tdre) in the bdlc state vector register (bsvr) is cleared to allow lo wer priority interrupt s to occur. (see 27.6.4 bdlc state vector register .) 1 = transmit end-of-data (eod) symbol 0 = the teod bit will be cleared automatically at the rising edge of the first crc bit that is sent or if an error is detected. when teod is used to end an ifr transmission, teod is cleared when the bdlc receives back a valid eod symbol or an error condition occurs. byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 358 freescale semiconductor tsifr, tmifr1, and tmifr0 ? transmit in-frame response control bits these three bits control the type of in-frame re sponse being sent. the programmer should not set more than one of these control bits to a 1 at any given time. however, if more than one of these three control bits are set to 1, the priority encoding logic will force these register bits to a known value as shown in table 27-4 . for example, if 011 is written to tsifr, tmifr1, and tmifr0, then internally they will be encoded as 010. however, when t hese bits are read back, they will read 011. the bdlc supports the in-frame response (ifr) f eature of j1850 by setting these bits correctly. the four types of j1850 ifr are shown below. the purpose of the in-frame response modes is to allow multiple nodes to acknowledge receipt of the data by responding with their personal id or physical address in a concatenated manner after they have se en the eod symbol. if transmission arbitration is lost by a node while sending its response, it continues to transmit its id/address until observing its unique byte in the response stream. for vpw modulation, because the first bit of the ifr is always passive, a normalization bit (active) must be gener ated by the responder and sent prior to its id/address byte. when there are multiple responder s on the j1850 bus, only one normalization bit is sent which assists all other transmi tting nodes to sync up their response. figure 27-18. types of in-frame response (ifr) table 27-4. bdlc transmit in-frame response control bit priority encoding write/read tsifr write/read tmifr1 write/read tmifr0 actual tsifr actual tmifr1 actual tmifr0 000000 1xx100 01x010 001001 sof header data field crc eod type 0 ? no ifr header data field crc eod type 3 ? multiple bytes transmitted from a single responder header data field crc eod type 1 ? single byte transmitted from a single responder header data field crc eod type 2 ? single byte transmitted from multiple responders id1 id n ifr data field crc nb nb nb id sof sof sof eof eod eof eod eof eod eof (optional) nb = normalization bit id = identifier (usually the phy sical address of the responder(s)) header = specifies one of three frame lengths bdlc cpu interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 359 tsifr ? transmit single byte ifr with no crc (type 1 or 2) bit the tsifr bit is used to request the bdlc to transmit the byte in the bdlc data register (bdr, $003f) as a single byte ifr with no crc. typically, the by te transmitted is a unique identifier or address of the transmitting (responding) node. see figure 27-18 . 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transm it the appropriate normalization bit followed by the byte in the bdr. 0 = the tsifr bit will be cleared automatically, once the bdlc has successfully transmitted the byte in the bdr onto the bus, or teod is set, or an error is detected on the bus. if the programmer attempts to set the tsifr bit immediately after the eod symbol has been received from the bus, the tsifr bit will remain in the reset state and no attempt will be made to transmit the ifr byte. if a loss of arbitration occurs when the bdlc attempts to transmit and after the ifr byte winning arbitration completes transmission, the bdlc wi ll again attempt to transmit the bdr (with no normalization bit). the bdlc will c ontinue transmission attempts until an error is detected on the bus, or teod is set, or the bdlc transmission is successful. if loss or arbitration occurs in the last tw o bits of the ifr byte, two additional 1 bits will not be sent out because the bdlc will attempt to retr ansmit the byte in the transmit shift register after the irf byte winning arbitration completes transmission. tmifr1 ? transmit multiple byte ifr with crc (type 3) bit the tmifr1 bit requests the bdlc to transmit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr with crc or as a sing le byte ifr with crc. response ifr bytes are still subject to j1850 message length maximums (see j1850 frame format and figure 27-18 ). 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transm it the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr register. after teod has been set and the last ifr byte has been transmitted, the crc byte is transmitted. 0 = the tmifr1 bit will be cleared automatically ? once the bdlc has successfully transmitted the crc byte and eod symbol ? by the detection of an error on the multiplex bus or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr1 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 27.6.4 bdlc state vector register ) will occur similar to the ma in message transmit sequence. the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bdlc control register 2 (bcr2). th is will instruct the bdlc to tr ansmit a crc byte once the byte in the bdr is transmitted and then transmit an eod sym bol, indicating the end of the ifr portion of the message frame. however, if the programmer wishes to transmit a si ngle byte followed by a crc byte, the programmer should load the byte into the bdr before the eod symbol has been received, and then set the tmifr1 bit. once the tdre interrupt occurs, the programmer should then set the teod bit in the bcr2. this will result in the byte in the bdr being the only byte transmitted before the ifr crc byte, and no tdre interrupt will be generated. byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 360 freescale semiconductor if the programmer attempts to set the tmifr1 bit immediately after the eod symbol has been received from the bus, the tmifr1 bit will remain in the rese t state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is trans mitting any byte of a multiple byte ifr, the bdlc will go to the loss of arbitration state, set the appropriate flag, and cease transmission. if the bdlc loses arbitration during the ifr, the tmifr1 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitrat ion occurs in the last two bits of the ifr byte, two additional 1 bits will be sent out. note the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. tmifr0 ? transmit multiple byte ifr without crc (type 3) bit the tmifr0 bit is used to request the bdlc to trans mit the byte in the bdlc data register (bdr) as the first byte of a multiple byte ifr without crc. response ifr bytes are still subject to j1850 message length maximums (see j1850 frame format and figure 27-18 ). 1 = if this bit is set prior to a valid eod being received with no crc error, once the eod symbol has been received the bdlc will attempt to transm it the appropriate normalization bit followed by ifr bytes. the programmer should set teod after the last ifr byte has been written into the bdr register. after teod has been set, the last ifr byte to be transmitted will be the last byte which was written into the bdr register. 0 = the tmifr0 bit will be cleared automatically ; once the bdlc has succ essfully transmitted the eod symbol; by the detection of an error on the multiplex bus; or by a transmitter underrun caused when the programmer does not write another byte to the bdr after the tdre interrupt. if the tmifr0 bit is set, the bdlc will attempt to transmit the normalization symbol followed by the byte in the bdr. after the byte in the bdr has been loaded into the transmit shift register, a tdre interrupt (see 27.6.4 bdlc state vector register ) will occur similar to the main message transmit sequence. the programmer should then load the next byte of the ifr into the bdr for transmission. when the last byte of the ifr has been loaded into the bdr, the programmer should set the teod bit in the bcr2. this will instruct the bdlc to transmit an eod sym bol once the byte in the bdr is transmitted, indicating the end of the ifr portion of the message frame. the bdlc will not append a crc when the tmifr0 is set. if the programmer attempts to set the tmifr0 bit after the eod symbol has been received from the bus, the tmifr0 bit will remain in the reset state, and no attempt will be made to transmit an ifr byte. if a loss of arbitration occurs when the bdlc is transmitting, the tmifr0 bit will be cleared and no attempt will be made to retransmit the byte in the bdr. if loss of arbitrat ion occurs in the last two bits of the ifr byte, two additional 1 bits (active short bits) will be sent out. note the extra logic 1s are an enhancement to the j1850 protocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. bdlc cpu interface mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 361 27.6.4 bdlc state vector register this register is provided to substantially decreas e the cpu overhead associated with servicing interrupts while under operation of a multiplex protocol. it provides an index offset that is directly related to the bdlc?s current state, which can be used with a us er-supplied jump table to rapidly enter an interrupt service routine. this eliminates the need for the us er to maintain a duplicate state machine in software. i0, i1, i2, and i3 ? interrupt source bits these bits indicate the source of the interrupt requ est that currently is pending. the encoding of these bits are listed in table 27-5 . bits i0, i1, i2, and i3 are cleared by a read of the bsvr except when the bdlc data register needs servicing (rdrf, rxifr, or tdre conditions). rxif r and rdrf can be cleared only by a read of the bsvr followed by a read of the bdlc data register (bdr). tdre can either be cleared by a read of the bsvr followed by a write to the bdlc bdr or by setting the teod bit in bcr2. address: $003e bit 7654321bit 0 read:0 0 i3i2i1i0 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 27-19. bdlc state vector register (bsvr) table 27-5. bdlc interrupt sources bsvr i3 i2 i1 i0 interrupt source priority $00 0000 no interrupts pending 0 (lowest) $04 0001 received eof 1 $08 0010 received ifr byte (rxifr) 2 $0c 0011 bdlc rx data register full (rdrf) 3 $10 0100 bdlc tx data register empty (tdre) 4 $14 0101 loss of arbitration 5 $18 0110 cyclical redu ndancy check (crc) error 6 $1c 0111 symbol invalid or out of range 7 $20 1000 wakeup 8 (highest) byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 362 freescale semiconductor upon receiving a bdlc interrupt, the user can read the value within the bsvr, transferring it to the cpu?s index register. the value can then be used to index into a jump table, with entries four bytes apart, to quickly enter the appropriate service routine. for example: note the nops are used only to align t he jmps onto 4-byte boundaries so that the value in the bsvr can be used intact. each of the service routines must end with an rti instruction to guarantee correct continued operation of the device. note also that the first entry can be omitted since it corresponds to no interrupt occurring. the service routines should clear all of the sources t hat are causing the pending interrupts. note that the clearing of a high priority interrupt may still leave a lo wer priority interrupt pending, in which case bits i0, i1, and i2 of the bsvr will then reflect the source of the remaining interrupt request. if fewer states are used or if a different software app roach is taken, the jump table can be made smaller or omitted altogether. 27.6.5 bdlc data register this register is used to pass the data to be transmitted to the j1850 bus from the cpu to the bdlc. it is also used to pass data received from the j1850 bus to the cpu. each data byte (after the first one) should be written only after a tx data register empty (tdre) state is indicated in the bsvr. data read from this register will be the last data byte received from the j1850 bus. this received data should only be read after an rx data register full (rdrf) interrupt has occurred. (see 27.6.4 bdlc state vector register ) service ldx bsvr fetch state vector number jmp jmptab,x enter service routine, * (must end in rti) * jmptab jmp serve0 service condition #0 nop jmp serve1 service condition #1 nop jmp serve2 service condition #2 nop * jmp serve8 service condition #8 end address: $003f bit 7654321bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: reset: unaffected by reset figure 27-20. bdlc data register (bdr) low-power modes mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 363 the bdr is double buffered via a transmit shadow regi ster and a receive shadow register. after the byte in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. once the trans mit shift register has shifted the first bit out, the tdre flag is set, and the shadow register is ready to accept the next data byte. the receive shadow register works similarly. once a complete byte has been received, the receive shift register stores the newly received byte into the receive shadow register. the rdrf flag is set to indicate that a new byte of data has been received. the programmer has one bdlc byte reception time to read the shadow register and clear the rdrf flag before the shadow regist er is overwritten by the newly received byte. to abort an in-progress transmission, the programmer should stop loading data into the bdr. this will cause a transmitter underrun error and the bdlc automat ically will disable the transmitter on the next non-byte boundary. this means that the earliest a tr ansmission can be halted is after at least one byte plus two extra logic 1s have been transmitted. the receiver will pick this up as an error and relay it in the state vector register as an invalid symbol error. note the extra logic 1s are an enhancement to the j1850 pr otocol which forces a byte boundary condition fault. this is helpful in preventing noise from going onto the j1850 bus from a corrupted message. 27.7 low-power modes the following information concerns wait mode and stop mode. 27.7.1 wait mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a wait instruction and the wcm bit in bdlc control register 1 (bcr1) is previously clear. in bdlc wait mode, the bdlc cannot drive any data. a subsequent successfully received message, including one that is in progress at the time that this mode is entered, will cause the bdlc to wake up and generate a cpu interrupt request if the interrupt enable (ie) bit in the bdlc control register 1 (bcr1) is previously set. (see 27.6.2 bdlc control register 1 for a better understanding of ie.) this results in less of a power saving, but the bdlc is guaranteed to receive correctly the message which woke it up, since the bdlc internal operating clocks are kept running. note ensuring that all transmissions are complete or aborted before putting the bdlc into wait mode is important. 27.7.2 stop mode this power-conserving mode is entered automatical ly from run mode whenever the cpu executes a stop instruction or if the cpu executes a wait inst ruction and the wcm bit in the bdlc control register 1 (bcr1) is previously set. this is the lowest power mode that the bdlc can enter. a subsequent passive-to-active transition on the j18 50 bus will cause the bdlc to wake up and generate a non-maskable cpu interrupt request. when a stop inst ruction is used to put the bdlc in stop mode, the bdlc is not guaranteed to correctly receive the message which woke it up, since it may take some time for the bdlc internal operating clocks to restart and stabilize. if a wait instruction is used to put the bdlc in stop mode, the bdlc is guaranteed to correctly receive the byte which woke it up, if and only if an end-of-frame (eof) has been detected prior to issuing the wait instruction by the cpu. otherwise, the bdlc will not correctly rece ive the byte that woke it up. byte data link controller (bdlc) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 364 freescale semiconductor if this mode is entered while the bdlc is receivi ng a message, the first subsequent received edge will cause the bdlc to wake up immediately, generat e a cpu interrupt request, and wait for the bdlc internal operating clocks to restart and stabilize before normal communications can resume. therefore, the bdlc is not guaranteed to receive that message correctly. note it is important to ensure all transmissions are complete or aborted prior to putting the bdlc into stop mode. mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 365 chapter 28 electrical specifications 28.1 electrical specifications 28.1.1 maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 28.1.4 5.0 volt dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating (1) 1. voltages are referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma reset and irq input voltage v hi v dd + 4.5 v electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 366 freescale semiconductor 28.1.2 functional operating range note for applications which use the lvi, freescale guarantees the functionality of the device down to the lvi trip point (v lvi ) within the constraints outlined in chapter 16 low-voltage inhibit (lvi) . 28.1.3 thermal characteristics rating symbol value unit operating temperature range (1) 1. t a (max) = 125 c for part suffix mfu/mfn t a (max) = 105 c for part suffix vfu/vfn t a (max) = 85 c for part suffix cfu/cfn t a ?40 to t a (max) c operating voltage range v dd 5.0 0.5 v characteristic symbol value unit thermal resistance qfp (64 pins) ja 70 c/w thermal resistance plcc (52 pins) ja 50 c/w i/o pin power dissipation p i/o user determined w power dissipation (see note 1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (see note 2) k p d x (t a + 273 c) + (p d 2 x ja ) w/ c average junction temperature t j t a + p d x ja c 1. power dissipation is a function of temperature. 2. k is a constant unique to the device. k can be determined from a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 367 28.1.4 5.0 volt dc elec trical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40c to +t a (max), unless otherwise noted. symbol min typical max unit output high voltage (i load = ?2.0 ma) all ports (i load = ?5.0 ma) all ports v oh v dd ?0.8 v dd ?1.5 ? ? ? ? v total source current i oh (tot) ??10ma output low voltage (i load = 1.6 ma) all ports (i load = 10.0 ma) all ports v ol ? ? ? ? 0.4 1.5 v total sink current i ol (tot) ??15ma input high voltage all ports, irq s, rst , osc1 v ih 0.7 x v dd ? v dd v input low voltage all ports, irq s, rst , osc1 v il v ss ? 0.3 x v dd v v dd supply current run (2) wait (3) stop (4) lvi enabled, t a = 25c lvi disabled, t a = 25c lvi enabled, ?40c to +125c lvi disabled, ?40c to +125c 2. run (operating) i dd measured using external s quare wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as i nputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. typical values at midpoint of voltage range, 25c only. 3. wait i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 vdc from rail. no dc loads. less than 100 pf on all outputs, c l = 20 pf on osc2. all ports configured as input s. osc2 capacitance linearly affects wait i dd . measured with all modules enabled. typical values at midpoint of voltage range, 25c only. 4. stop i dd measured with osc1 = v ss . i dd (5) 5. although i dd is proportional to bus frequency, a current of se veral ma is present even at very low frequencies. ? ? ? ? ? ? 25 14 100 35 35 20 400 50 500 100 ma ma a a a a i/o ports hi-z leakage current i l ?1 ? 1 a input current i in ?1 ? 1 a capacitance ports (as input or output) c out c in ? ? ? 12 8 pf low-voltage reset inhibit (trip) (recover) v lv i 3.80 ? ? ? ? 4.49 v por rearm voltage (6) 6. maximum is highest vo ltage that por is guaranteed. v por 0 ? 200 mv por reset voltage (7) 7. maximum is highest vo ltage that por is possible. v porrst 0 ? 800 mv por rise time ramp rate (8) 8. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms high cop disable voltage (9) 9. see 15.8 cop module during break interrupts . v hi applied to rst . v hi v dd + 3.0 ? v dd + 4.5 v monitor mode entry voltage on irq (10) 10. see monitor mode description within chapter 15 computer operating properly (cop) . v hi applied to irq or rst v hi v dd + 3.0 ? v dd + 4.5 v pull resistor (kbd[4:0]) r pu ? 100 ? k electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 368 freescale semiconductor 28.1.5 control timing 28.1.6 adc characteristics characteristic (1) 1. v dd = 5.0 vdc 0.5v, v ss = 0 vdc, t a = ?40 c to t a (max), unless otherwise noted. symbol min max unit bus operating frequency (4.5?5.5 v ? v dd only) f bus ?8.4mhz r st pulse width low t rl 1.5 ? t cyc irq interrupt pulse width low (edge-triggered) t ilhi 1.5 ? t cyc irq interrupt pulse period t ilil note 4 ? t cyc 16-bit timer (2) input capture pulse width (3) input capture period 2. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. refer to table 25-2. mode, edge, and level selection and supporting note. t th, t tl t tltl 2 note (4) 4. the minimum period t tltl or t ilil should not be less than the number of cycles it takes to execute the capture interrupt service routine plus tbd t cyc . ? ? t cyc mscan wake-up filter pulse width (5) 5. the minimum pulse width to wake up the mscan mo dule is guaranteed by design but not tested. t wup 25 s characteristic (1) 1. v dd = 5.0 vdc 0.5 v, v ss = 0 vdc, v dda /v ddaref = 5.0 vdc 0.5 v, v ssa = 0 vdc, v refh = 5.0 vdc 0.5 v min max unit comments resolution 8 8 bits absolute accuracy (v refl = 0 v, v dda /v ddaref = v refh = 5 v 0.5 v) ?1 +1 lsb includes quantization conversion range (2) 2. source impedances greater than 10 k adversely affect internal rc charging time during input sampling. v refl v refh v v refl = v ssa power-up time 16 17 s conversion time period input leakage (3) (ports b and d) 3. the external system error caused by input l eakage current is approximatel y equal to the product of r source and input current. ?1 1 a conversion time 16 17 adc clock cycles includes sampling time monotonicity inherent within total error zero input reading 00 01 hex v in = v refl full-scale reading fe ff hex v in = v refh sample time (2) 5? adc clock cycles input capacitance ? 8 pf not tested adc internal clock 500 k 1.048 m hz tested only at 1 mhz analog input voltage v refl v refh v electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 369 28.1.7 5.0 vdc 0.5 v serial peripheral interface (spi) timing num (1) 1. item numbers refer to dimensio ns in figure 28-1 and figure 28-2 . characteristic (2) 2. all timing is shown with respect to 30% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins. symbol min max unit operating frequency (3) master slave 3. f bus = the currently active bus frequency for the microcontroller. f bus( m ) f bus( s ) f bus /128 dc f bus /2 f bus mhz 1 cycle time master slave t cyc( m ) t cyc( s ) 2 1 128 ? t cyc 2 enable lead time t lead 15 ? ns 3 enable lag time t lag 15 ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 100 50 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 100 50 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (4) cpha = 0 cpha = 1 4. time to data active from high-impedance state. t a(cp0) t a(cp1) 0 0 40 20 ns 9 slave disable time (hold time to high-impedance state) t dis ?25ns 10 enable edge lead time to data valid (5) master slave 5. with 100 pf on all spi pins. t ev(m) t ev(s) ? ? 10 40 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 5 ? ? ns 12 data valid master (before capture edge) t v(m) 90 ? ns 13 data hold time (outputs) master (before capture edge) t ho(m) 100 ? ns electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 370 freescale semiconductor figure 28-1. spi master timing diagram note note: this first cloc k edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high. msb in ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) mosi (output) note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 13 12 13 electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 371 figure 28-2. spi slave timing diagram note: not defined but normally msb of character just received slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (input) mosi (output) 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 372 freescale semiconductor 28.1.8 cgm operating conditions 28.1.9 cgm component information characteristic symbol min typ max unit comments operating voltage v dda v dd ?0.3 ? v dd +0.3 v v ssa v ss ?0.3 ? v ss +0.3 v crystal reference frequency f cgmrclk 14.91528mhz module crystal reference frequency f cgmxclk ?4.9152?mhz same frequency as f cgmrclk range nom. multiplier f nom ?4.9152?mhz vco center-of-range frequency f cgmvrs 4.9152 ? note (1) 1. f cgmvrs is a nominal value described and calculated as an example in chapter 10 clock generator module (cgm) for the desired vco operating frequency, f cgmvclk . mhz vco operating frequency f cgmvclk 4.9152 ? 32.0 description symbol min typ max unit comments crystal load capacitance c l ???? consult crystal manufacturer?s data crystal fixed capacitance c1 ? 2 x cl ? ? consult crystal manufacturer?s data crystal tuning capacitance c2 ? 2 x cl ? ? consult crystal manufacturer?s data filter capacitor multiply factor c fact ? 0.0154 ? f/s v filter capacitor c f ? c fact x (v dda /f xclk ) ?? see 10.4.3 external filter capacitor pin (cgmxfc) bypass capacitor c byp ?0.1? f cbyp must provide low ac impedance from f = f cgmxclk /100 to 100 x f cgmvclk , so series resistance must be considered. electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 373 28.1.10 cgm acquisition/lock time information description (1) 1. v dd = 5.0 vdc 0.5 v, v ss = 0 vdc, t a = ?40c to t a (max), unless otherwise noted. symbol min typ (2) 2. conditions for typical and maximu m values are for run mode with f cgmxclk = 8 mhz, f busdes = 8 mhz, n = 4, l = 7, discharged c f = 15 nf, v dd = 5 vdc. max (2) unit notes manual mode time to stable t acq ? (8 x v dda ) / (f cgmxclk x k acq) ?s if c f chosen correctly manual stable to lock time t al ? (4 x v dda ) / (f cgmxclk x k trk ) ?s if c f chosen correctly manual acquisition time t lock ? t acq +t al ?s tracking mode entry frequency tolerance d trk 0? 3.6 % acquisition mode entry frequency tolerance d unt 6.3 ? 7.2 % lock entry freq. tolerance d lock 0? 0.9 % lock exit freq. tolerance d unl 0.9 ? 1.8 % reference cycles per acquisition mode measurement n acq ?32?? reference cycles per tracking mode measurement n trk ?128?? automatic mode time to stable t acq n acq /f xclk (8 x v dda ) / (f xclk x k acq) s if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4 x v dda ) / (f xclk x k trk ) ?s if c f chosen correctly automatic lock time t lock ?0.6525ms pll jitter, deviation of average bus frequency over 2 ms (3) 3. guaranteed by not tested. refer to chapter 10 clock generator module (cgm) for guidance on the use of the pll. 0? (f crys ) x (.025%) x (n/4) % n = vco freq. mult. k value for automatic mode time to stable k acq ?0.2?? k value k trk ? 0.004 ? ? electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 374 freescale semiconductor 28.1.11 timer module characteristics 28.1.12 ram memory characteristics 28.1.13 eeprom memory characteristics characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic symbol min max unit ram data retention voltage v rdr 0.7 ? v characteristic symbol min max unit eeprom programming time per byte t eepgm 10 ? ms eeprom erasing time per byte t eebyte 10 ? ms eeprom erasing time per block t eeblock 10 ? ms eeprom erasing time per bulk t eebulk 10 ? ms eeprom programming voltage discharge period t eefpv 100 ? s number of programming operations to the same eeprom byte before erase (1) 1. programming a byte more times than the s pecified maximum may affect the data integrity of that byte. the byte must be erased before it can be programmed again. ??8? eeprom write/erase cycles @ 10 ms write time ? 10,000 ? cycles eeprom data retention after 10, 000 write/erase cycles ? 10 ? years eeprom programming maximum time to ?auto? bit set ? ? 500 s eeprom erasing maximum time to ?auto? bit set ? ? 8 ms electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 375 28.1.14 flash memory characteristics characteristic symbol min max unit flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8.4m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (m in ), there is no erase-disturb, but it reduc es the endurance of the flash memory. 1?ms flash mass erase time t m erase (3) 3. if the mass erase time is longer than t merase (m in ) , there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash pgm/erase to hven set up time t nvs 10 ? s flash high voltage hold time t nvh 5? s flash high voltage hold time (mass) t nvh l 100 ? s flash program hold time t pgs 5? s flash program time t prog 30 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump by clearing hven t o logic 0. 1 s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage progra mming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + ( t prog x 64) t hv max. ?4ms flash row erase endurance (6) 6. the minimum row erase endurance value specifies each row of t he flash memory is guaranteed to work for at least this many er ase cycles. 10,000 ? cycles flash row program endurance (7) 7. the minimum row program endurance value s pecifies each row of the flash memory is guaranteed to work for at least this many program cycles. 10,000 ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operat ing temperature range for at leas t the minimum time specified. 10 ? years electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 376 freescale semiconductor 28.1.15 bdlc transmitte r vpw symbol timings 28.1.16 bdlc receiver vpw symbol timings characteristic (1), (2) (3) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. see figure 28-3 . 3. transmit timing dependent upon bard regist er matching physical transceiver timing. number symbol min typ max unit passive logic 0 10 t tvp1 62 64 66 s passive logic 1 11 t tvp2 126 128 130 s active logic 0 12 t tva1 126 128 130 s active logic 1 13 t tva2 62 64 66 s start-of-frame (sof) 14 t tva3 198 200 202 s end-of-data (eod) 15 t tvp3 198 200 202 s end-of-frame (eof) 16 t tv4 278 280 282 s inter-frame separator (ifs) 17 t tv6 298 300 ? s characteristic (1), (2), (3) 1. f bdlc = 1.048576 or 1.0 mhz, v dd = 5.0 v 10%, v ss = 0 v 2. t he receiver symbol timing boundaries are subject to an uncertainty of 1 t bdlc s due to sampling considerations. 3. see figure 28-3 . number symbol min typ max unit passive logic 0 10 t trvp1 34 64 96 s passive logic 1 11 t trvp2 96 128 163 s active logic 0 12 t trva1 96 128 163 s active logic 1 13 t trva2 34 64 96 s start-of-frame (sof) 14 t trva3 163 200 239 s end-of-data (eod) 15 t trvp3 163 200 239 s end-of-frame (eof) 16 t trv4 239 280 320 s break 18 t trv6 280 ? ? s electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 377 figure 28-3. bdlc variable pulse width modulation (vpw) symbol timing 28.1.17 bdlc transmitter dc electrical characteristics 28.1.18 bdlc receiver dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted symbol min max unit bdtxd output low voltage (ibdtxd = 1.6 ma) v oltx ?0.4 v bdtxd output high voltage (ibdtx = ?800 a) v ohtx v dd ?0.8 ?v characteristic (1) 1. v dd = 5.0 vdc + 10%, v ss = 0 vdc, t a = ?40 o c to +125 o c, unless otherwise noted symbol min max unit bdrxd input low voltage v ilrx v ss 0.3 x v dd v bdrxd input high voltage v ihrx 0.7 x v dd v dd v bdrxd input low current i ilbdrxi ?1 +1 a bdrxd input high current i hbdrx ?1 +1 a 13 11 10 12 16 14 sof 15 18 0 0 1 1 eod brk 0 eof electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 378 freescale semiconductor 28.2 mechanical specifications 28.2.1 51-pin plastic lea ded chip carrier (plcc) mechanical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 379 28.2.2 64-pin quad flat pack (qfp) electrical specifications mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 380 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 381 appendix a mc68hc908as60 and mc68hc908az60 a.1 changes from the mc68hc908as60 and mc68hc 908az60 (non-a suffix devices) a.1.1 specification specifications for mc68hc908as60a and mc68hc908a z60a devices have been integrated, reflecting the many commonalties. a.1.2 flash a.1.2.1 flash architecture flash-1 and flash-2 are made from a new nonvolatil e memory (nvm) technology. the architecture is now arranged in pages of 128 bytes and 2 rows per page. programming is now carried out on a whole row (64 bytes) at a time. erasing is now carried out on a whole page (128 bytes) at a time. in this new technology an erased bit now reads as a logic 1 and a programmed bit now reads as a logic 0. a.1.2.2 flash control registers flash-1 control register is moved from $fe0b to $ ff88. flash-2 control register is moved from $fe11 to $fe08. bits 4 to 7 in the flash control register s are no longer used since clock control is now achieved automatically and erasing of variable block sizes is no longer a feature. bit 2 of the flash control registers no longer activates a so-called ?margin read? op eration but instead is the bit that controls a mass (bulk) erase operation. a.1.2.3 flash programming procedure programming of the flash is largely as before within the new architecture constraints outlined above. however, an extra dummy write operation to any address in the page is required prior to programming data into one of the two rows in the page. margin reading of programmed data is no longer required. nor is read / verify / re-pulse of the programming a requirement. a.1.2.4 flash programming time the most significant change resulting from the new flas h technology is that the byte programming time is reduced to a maximum of 40us. this represents several orders of magnitude improvement from the previous technology. mc68hc908as60 and mc68hc908az60 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 382 freescale semiconductor a.1.2.5 flash block protection the flash block protect registers are now 8-bit regist ers in place of 4-bit protecting array ranges that can be incremented by as little as 1 page (128 bytes) at a time as opposed to 8 kbytes at a time on previous mcus. users making use of the block protec t feature must change their block protect register. a further significant change is that high voltage (v hi ) is no longer needed on the irq pin to program or erase the flash block protect registers. a.1.2.6 flash endurance the flash endurance is now specified as 10,000 writ e / erase cycles as opposed to less than 1000 before. a.1.3 eeprom a.1.3.1 eeprom architecture like the flash, eeprom-1 and eeprom-2 are also made from a new nvm te chnology. however, unlike the flash, the bit polarity remains the same i.e. programmed=0, erased=1. the architecture and basic programming and erase operations are unchanged. a.1.3.2 eeprom clock source and prescaler the first major difference on the new eeprom is that it requires a constant time base source to ensure secure programming and erase operations. this is d one by firstly selecting wh ich clock source is going to drive the eedivg clock divider input using a new bit 7 introduced ont o the config-2 register $fe09. next the divide ratio from this source has to be set by programming an 11-bit time base pre-scalar into bits spread over two new registers, eedivxh and eedivxl (where x=1 or 2 for eeprom-1 or eeprom-2 arrays). the eedivxh and eedivxl registers are volatile. howe ver, they are loaded upon reset by the contents of duplicate nonvolatile eedivxhnvr and eedivxlnvr registers much in the same way as the array control registers (eeacrx) interact with the nonvolat ile registers (eenvrx) for configuration control on the existing revision. as a result of the new eedi v clock described above bit 7 (eebclk) of the eeprom control registers (eecrx) is no longer used. a.1.3.3 eeprom auto programming & erasing the second major change to the eeprom is the inclus ion in the eeprom control registers (eecrx) of an auto function using previously unused bit 1 of these registers. the auto function enables the logic of the mcu to automatically use th e optimum programming or erasing time for the eeprom. if using auto the user does not need to wait for the normal minimum specified programming or erasing ti me. after setting the eepgm bit as normal the user just has to poll that bit again, waiting for the mcu to clear it i ndicating that programming or erasing is complete. changes from the mc68hc908as60 and mc68hc908az60 (non-a suffix devices) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 383 a.1.4 config-2 config-2 register $fe09 has 2 new bi ts activated. bit 3 is now a silicon hard set bit, which identifies this new a-suffix silicon (1) from the previous non-a suffi x silicon (0). bit 7 is now an eeprom time base divider clock select bit selecting the reference cloc k source for the eeprom time base divider module (refer to eeprom changes described above). a.1.5 keyboard interrupt the keyboard module is now a feature of the mc68 hc908as60a in 64-qfp pa ckage whereas previously it was only a feature of the az device. vector addresses $ffd2 and $ffd3 are now in the as memory map in support of this option. a.1.6 current consumption current consumption will be signifi cantly lower in many applications . although maximum specifications are still very dependent upon fabrication process vari ation and configuration of the mcu in the target application, additional values have been added to the i dd specifications to provide typical current consumption data. please see chapter 28 electrical specifications for further details. a.1.7 illegal address reset only an opcode fetch from an illegal address will gen erate an illegal address reset. data fetches from unmapped addresses will not generate a reset. a.1.8 monitor mode entr y and cop disable voltage the monitor mode entry and cop disable voltage specifications (v hi ) have been increased. please see chapter 28 electrical specifications for details. a.1.9 low-voltage inhibit (lvi) the low-voltage inhibit (lvi) specificat ions for trip and recovery voltage (v lvi ) have been altered based upon module performance on silicon. please see for chapter 28 electrical specifications details. mc68hc908as60 and mc68hc908az60 mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 384 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 385 appendix b MC68HC908AZ60E b.1 introduction the MC68HC908AZ60E is a reduced emc version of the mc68hc908az60a. every care has been taken to insure compatibility with the mc68hc9 08az60a. some additional features are available, however the default state of all affected modules match the mc68hc908az60a functionality. the reset state of all MC68HC908AZ60E registers match the mc68hc908az60a except for some reserved memory locations. although significant design ch anges have been made to improve the radiated rf emissions from the mcu, all electrical specificati ons are equal to or better than the mc68hc908az60a. slew rate controlled outputs have been added to all the general purpose i/o pins as well as the ptc2/mclk, pte5/miso, pte6/mosi, and pte7/spsck pins. table b-1. external pins summary (sheet 1 of 3) pin name function driver type hysteresis (1) reset state pta7?pta0 general-purpose i/o dual state no input hi-z ptb7/atd7?ptb0/atd0 general-purpose i/o adc channels dual state no input hi-z ptc5?ptc3 general-purpose i/o dual state no input hi-z ptc2/mclk general-purpose i/o mclk output dual state no input hi-z ptc1?ptc0 general-purpose i/o dual state no input hi-z ptd7 general purpose i/o dual state no input hi-z ptd6/atd14/taclk adc channel general-purpose i/o adc channel/timer external input clock dual state yes, taclk input hi-z ptd5/atd13 adc channel general-purpose i/o adc channel dual state no input hi-z ptd4/atd12/tbclk adc channel general-purpose i/o adc channel/timer external input clock dual state yes, tbclk input hi-z ptd3/atd11?ptd0/atd8 adc channels general-purpose i/o adc channel dual state no input hi-z pte7/spsck general-purpose i/o spi clock dual state open drain yes, spsck input hi-z pte6/mosi general-purpose i/o spi data path dual state open drain yes, mosi input hi-z pte5/miso general-purpose i/o spi data path dual state open drain yes, miso input hi-z MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 386 freescale semiconductor pte4/ss general-purpose i/o spi slave select dual state yes, ss input hi-z pte3/tach1 general-purpose i/o timer a channel 1 dual state yes, tach1 input hi-z pte2/tach0 general-purpose i/o timer a channel 0 dual state yes, tach0 input hi-z pte1/rxd general-purpose i/o sci receive data dual state yes, rxd input hi-z pte0/txd general-purpose i/o sci transmit data dual state no input hi-z ptf6 general-purpose i/o dual state no input hi-z ptf5/tbch1 general-purpose i/o timer b channel 1 dual state yes, tbch1 input hi-z ptf4/tbch0 general-purpose i/o timer b channel 0 dual state yes, tbch0 input hi-z ptf3/tach5 general-purpose i/o timer a channel 5 dual state yes, tach5 input hi-z ptf2/tach4 general-purpose i/o timer a channel 4 dual state yes, tach4 input hi-z ptf1/tach3 general-purpose i/o timer a channel 3 dual state yes, tach3 input hi-z ptf0/tach2 general-purpose i/o timer a channel 2 dual state yes, tach2 input hi-z ptg2/kbd2?ptg0/kbd0 general-purpose i/o keyboard wakeup pin dual state yes, kbd input hi-z pth1/kbd4? pth0/kbd3 general-purpose i/o keyboard wakeup pin dual state yes, kbd input hi-z v dd chip power supply n/a n/a n/a v ss chip ground n/a n/a n/a v dda cgm analog power supply n/a n/a n/a v ssa cgm analog ground n/a n/a n/a v ddaref adc power supply n/a n/a n/a a vss /v refl adc ground/adc reference low voltage n/a n/a n/a v refh adc reference high voltage n/a n/a n/a osc1 external clock in n/a n/a input hi-z osc2 external clock out n/a n/a output cgmxfc pll loop filter cap n/a n/a n/a table b-1. external pins summary (sheet 2 of 3) pin name function driver type hysteresis (1) reset state detailed memory map changes (mc68hc908as60a references have been removed) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 387 b.2 detailed memory map changes (mc68hc908a s60a references have been removed) every care has been taken to insure compatibilit y with the mc68hc908az60a; however, the following memory map changes have been made. $fe0b is now configuration register 3 (config3) irq external interrupt request n/a yes input hi-z rst external reset open drain yes output low canrx can serial input n/a yes input hi-z cantx can serial output output no output hi-z 1. hysteresis is not 100% tested but is typically a minimum of 300 mv. $0000 i/o registers 80 bytes $004f $0050 ram-1 1024 bytes $044f $0450 flash-2 176 bytes $04ff $0500 can control and message buffers 128 bytes $057f $0580 flash-2 128 bytes $05ff $0600 eeprom-2 512 bytes $07ff $0800 eeprom-1 512 bytes $09ff figure b-1. MC68HC908AZ60E memory map (sheet 1 of 3) table b-1. external pins summary (sheet 3 of 3) pin name function driver type hysteresis (1) reset state MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 388 freescale semiconductor $0a00 ram-2 1024 bytes $0dff $0e00 flash-2 29,184 bytes $7fff $8000 flash-1 32,256 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved $fe06 reserved $fe07 reserved $fe08 flash-2 control register (fl2cr) $fe09 configuration write-once register (config-2) $fe0a reserved $fe0b configuration write-once register (config-3) $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (bscr) $fe0f lvi status register (lvisr) $fe10 eeprom-1eedivh nonvolat ile register (ee1divhnvr) $fe11 eeprom-1eedivl nonvolat ile register (ee1divlnvr) $fe12 reserved $fe13 reserved $fe14 reserved $fe15 reserved $fe16 reserved $fe17 reserved $fe18 reserved $fe19 reserved $fe1a eeprom-1 ee divider high register(ee1divh) $fe1b eeprom-1 ee divider low register(ee1divl) $fe1c eeprom-1 eeprom nonvolatile register (ee1nvr) $fe1d eeprom-1 eeprom control register (ee1cr) $fe1e reserved $fe1f eeprom-1 eeprom array configuration register (ee1acr) figure b-1. MC68HC908AZ60E memory map (sheet 2 of 3) detailed memory map changes (mc68hc908as60a references have been removed) mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 389 $fe20 monitor rom 256bytes $ff1f $ff20 $ff6f unimplemented 80 bytes $ff70 eeprom-2 eedivh nonvolat ile register (ee2divhnvr) $ff71 eeprom-2 eediv l nonvolatile regi ster (ee2divlnvr) $ff72 reserved $ff73 reserved $ff74 reserved $ff75 reserved $ff76 reserved $ff77 reserved $ff78 reserved $ff79 reserved $ff7a eeprom-2 ee divider high register (ee2divh) $ff7b eeprom-2 ee divider low register (ee2divl) $ff7c eeprom-2 eeprom nonvolatile register (ee2nvr) $ff7d eeprom-2 eeprom control register (ee2cr) $ff7e reserved $ff7f eeprom-2 eeprom array configuration register (ee2acr) $ff80 flash-1 block prot ect register (fl1bpr) $ff81 flash-2 block prot ect register (fl2bpr) $ff82 reserved 6 bytes $ff87 $ff88 flash-1 control register (fl1cr) $ff89 reserved $ff8a reserved $ff8b reserved 64 bytes $ffcb $ffcc $ffff vectors 52 bytes see table b-2 figure b-1. MC68HC908AZ60E memory map (sheet 3 of 3) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 390 freescale semiconductor b.3 i/o section addresses $0000?$004f, shown in figure b-2 , contain the i/o data, status, and control registers. differences from the mc68hc908az60a are shown in bold text. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddr2 ddrd1 ddrd0 write: $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: $0009 port f data register (ptf) read: 0 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: $000a port g data register (ptg) read:00000 ptg2 ptg1 ptg0 write: $000b port h data register (pth) read:000000 pth1 pth0 write: $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: $000d data direction register f (ddrf) read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: $000e data direction register g (ddrg) read:00000 ddrg2 ddrg1 ddrg0 write: $000f data direction register h (ddrh) read:000000 ddrh1 ddrh0 write: $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: = unimplemented r = reserved figure b-2. i/o data, status and control registers (sheet 1 of 4) i/o section mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 391 $0012 spi data register (spdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: $0017 sci status register 2 (scs2) read:000000bkfrpf write: $0018 sci data register (scdr) read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: $001a irq status and control register (iscr) read:0000irqf0 imask mode write: rack $001b keyboard status and control register (kbscr) read:0000keyf0 imaskk modek write: ackk $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: $001f configuration write-once register (config-1) read: lvistop r lvirst lvipwr ssrec copl stop copd write: $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r $0021 keyboard interrupt enable register (kbier) read:000 kbie4 kbie3 kbie2 kbie1 kbie0 write: $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $0023 timer a counter register low (tacntl) read:bit 7654321bit 0 write: $0024 timer a modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure b-2. i/o data, status and control registers (sheet 2 of 4) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 392 freescale semiconductor $0025 timer a modulo register low (tamodl) read: bit 7654321bit 0 write: $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0028 timer a channel 0 register low (tach0l) read: bit 7654321bit 0 write: $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: $002b timer a channel 1 register low (tach1l) read: bit 7654321bit 0 write: $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: $002e timer a channel 2 register low (tach2l) read: bit 7654321bit 0 write: $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0031 timer a channel 3 register low (tach3l) read: bit 7654321bit 0 write: $0032 timer a channel 4 status and control register (tasc4) read: ch4f ch4ie ms4b ms4a els4b els4a tov4 ch4max write: 0 $0033 timer a channel 4 register high (tach4h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0034 timer a channel 4 register low (tach4l) read: bit 7654321bit 0 write: $0035 timer a channel 5 status and control register (tasc5) read: ch5f ch5ie 0 ms5a els5b els5a tov5 ch5max write: 0 $0036 timer a channel 5 register high (tach5h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0037 timer a channel 5 register low (tach5l) read: bit 7654321bit 0 write: $0038 analog-to-digital status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure b-2. i/o data, status and control registers (sheet 3 of 4) i/o section mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 393 $0039 analog-to-digital data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: $003a analog-to-digital input clock register (adiclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: rrrr $0040 timer b status and control register (tbscr) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $0042 timer b counter register low (tbcntl) read:bit 7654321bit 0 write: $0043 timer b modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: $0044 timer b modulo register low (tbmodl) read: bit 7654321bit 0 write: $0045 timer b ch0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 $0046 timer b ch0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: $0047 timer b ch0 register low (tbch0l) read: bit 7654321bit 0 write: $0048 timer b ch1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 $0049 timer b ch1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: $004a timer b ch1 register low (tbch1l) read: bit 7654321bit 0 write: $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: $004d pit counter register low (pcntl) read:bit 7654321bit 0 write: $004e pit modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: $004f pit modulo register low (pmodl) read: bit 7654321bit 0 write: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure b-2. i/o data, status and control registers (sheet 4 of 4) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 394 freescale semiconductor b.4 additional status and control registers selected addresses in the range $fe00 to $ff88 cont ain additional status and control registers as shown in figure b-3 . a noted exception is the cop control register (copctl) at address $ffff. differences from the mc68hc908az60a are shown in bold text. addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr bw r write: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: $fe08 flash-2 control register (fl2cr) read: write: 0000 hven verf erase pgm $fe09 configuration write-once register (config-2) read: eediv- clk rrmscand at60a rrazxx write: r $fe0b configuration write-once register (config-3) read: rrrrrrspisrdr write: $fe0c break address register low (brkl) read: bit 15 14 13 12 11 10 9 bit 8 write: $fe0d break address register low (brkl) read: bit 7654321bit 0 write: $fe0e break status and control register (brkscr) read: brke brka 000000 write: $fe0f lvi status register (lvisr) read: lviout 0000000 write: $fe10 ee1div hi nonvolatile register (ee1divhnvr) read: write: eedivs- ecd rrrreediv10eediv9eediv8 $fe11 ee1div lo nonvolatile register (ee1divlnvr) read: write: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 $fe1a ee1div divider high register (ee1divh) read: write: eedivs- ecd 0000 eediv10 eediv9 eediv8 $fe1b ee1div divider low register (ee1divl) read: write: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 $fe1c eeprom-1 nonvolatile register (ee1nvr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $fe1d eeprom-1 control register (ee1cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: $fe1f eeprom-1 array configuration register (ee1acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: = unimplemented r = reserved figure b-3. additional status and control registers (sheet 1 of 2) additional status and control registers mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 395 $ff70 ee2div hi nonvolatile register (ee2divhnvr) read: eedivs- ecd rrrreediv10eediv9eediv8 $ff71 ee2div lo nonvolatile register (ee2divlnvr) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $ff7a ee2div divider high register (ee2divh) read: eedivs- ecd 0000 eediv10 eediv9 eediv8 write: $ff7b ee2div divider low register (ee2divl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: $fe7c eeprom-2 nonvolatile register (ee2nvr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $fe7d eeprom-2 control register (ee2cr) read: unused 0 eeoff eeras1 eeras0 eelat auto eepgm write: $fe7f eeprom-2 array configuration register (ee2acr) read: unused unused unused eeprtct eebp3 eebp2 eebp1 eebp0 write: $ff80 flash-1 block protect register (fl1bpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: $ff81 flash-2 block protect register (fl2bpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: $ff88 flash-1 control register (fl1cr) read: 0000 hven verf erase pgm write: $ffff cop control register (copctl) read: low byte of reset vector write: writing to $ffff clears cop counter addr.register name bit 7654321bit 0 = unimplemented r = reserved figure b-3. additional status and control registers (sheet 2 of 2) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 396 freescale semiconductor b.5 vector addresses and priority addresses in the range $ffcc to $ffff contain the user-specified vector locations. the vector addresses are shown in table b-2 . vector address MC68HC908AZ60E lowest priority $ffcc tima channel 5 vector (high) $ffcd tima channel 5 vector (low) $ffce tima channel 4 vector (high) $ffcf tima channel 4 vector (low) $ffd0 adc vector (high) $ffd1 adc vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda can transmit vector (high) $ffdb can transmit vector (low) $ffdc can receive vector (high) $ffdd can receive vector (low) $ffde can error vector (high) $ffdf can error vector (low) $ffe0 can wakeup vector (high) $ffe1 can wakeup vector (low) $ffe2 spi transmit vector (high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector (high) $ffe5 spi receive vector (low) $ffe6 timb overflow vector (high) $ffe7 timb overflow vector (low) $ffe8 timb ch1 vector (high) $ffe9 timb ch1 vector (low) $ffea timb ch0 vector (high) $ffeb timb ch0 vector (low) $ffec tima overflow vector (high) $ffed tima overflow vector (low) table b-2. vector addresses ordering information mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 397 b.6 ordering information this section contains instructions for ordering the MC68HC908AZ60E. b.6.1 mc order numbers $ffee tima ch3 vector (high) $ffef tima ch3 vector (low) $fff0 tima ch2 vector (high) $fff1 tima ch2 vector (low) $fff2 tima ch1 vector (high) $fff3 tima ch1 vector (low) $fff4 tima ch0 vector (high) $fff5 tima ch0 vector (low) $fff6 pit vector (high) $fff7 pit vector (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) highest priority $ffff reset vector (low) table b-3. mc order numbers mc order number operating temperature range MC68HC908AZ60Ecfu (64-pin qfp) ?40 c to + 85 c MC68HC908AZ60Evfu (64-pin qfp) ?40 c to + 105 c MC68HC908AZ60Emfu (64-pin qfp) ?40 c to + 125 c vector address MC68HC908AZ60E table b-2. vector addresses (continued) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 398 freescale semiconductor b.7 configuration register (config-3) this section describes the configuration regist er (config-3). this register is unused on the mc68hc908az60a. this register contains o ne bit that configures the following option: disables slew rate control for the spi pins the configuration register is a write-once register. once the register is written, further writes will have no effect until a reset occurs. spisrd ? spi slew rate disable this bit disables the slew rate contro lled outputs for sck, mosi, and miso pins. 1 = spi slew rate is disabled 0 = spi slew rate is enabled b.8 sci the incorrect operation, signified by the "note" in the idle characters paragraph of the sci section of this document has been corrected. the following note does not apply to the MC68HC908AZ60E. note when a break sequence is followed immedi ately by an idle character, this sci design exhibits a condition in wh ich the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or ni ne data bits (as defined by the m bit in scc1) of logic 0 and one half data bit length of logic 0 in the stop bit position followed immediately by the idle char acter. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. b.9 mscan the mscan08 errata on the mc68hc908az60a has been fixed on the MC68HC908AZ60E. for 32-bit and 16-bit identifier acceptance m odes, an extended id can frame with a stuff bit between id16 and id15 will not be rejected. no software work around is required. address: $fe0b bit 7654321bit 0 read: rrrrrrspisrdr write: reset:00000000 r= reserved figure b-4. configuration register (config-3) adc mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 399 b.10 adc this section explains the difference in functionality of the conversion complete bit (coco) in the adc10 status and control register (adcsc). writing adcsc aborts the current conversion and initiates a new conversion (if the adch[4:0] bits are equal to a value other than all 1s). coco ? conversion complete bit coco is a read-only bit which is set each time a conv ersion is completed. this bit is cleared whenever the status and control register is written or whenever the data register is read. 1 = conversion completed 0 = conversion not completed bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure b-5. adc10 status and control register (adcsc) MC68HC908AZ60E mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 400 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 401 revision history major change between revision 5.0 and revision 6.0 the following table lists the major change between the current revision of the mc68hc908az60a technical data book, rev 6.0, and the previous revision, rev 5.0. major changes between revisi on 5.0 and revision 4.0 the following table lists the major changes betw een the current revision of the mc68hc908az60a technical data book, rev 5.0, and the previous revision, rev 4.0. major changes between revisi on 4.0 and revision 3.0 the following table lists the major changes betw een the current revision of the mc68hc908az60a technical data book, rev 4.0, and the previous revision, rev 3.0. major changes between revisi on 3.0 and revision 2.0 the following table lists the major changes betw een the current revision of the mc68hc908az60a technical data book, rev 3.0, and the previous revision, rev 2.0. section affected description of change appendix b. MC68HC908AZ60E added chapter describing the MC68HC908AZ60E. section affected description of change throughout updated to meet freescale identity guidelines. chapter 24 keyboard module (kbi) addresses for kbscr and kbier registers corrected to $001b and $0021 repectively. chapter 28 electrical specifications updated values for 28.1.8 cgm operating conditions . section affected description of change electrical specifications updated case outline drawing for 64-pin quad flat pack (case 840b) section affected description of change keyboard module (kbd) in table 24-1, addresses for kbscr and kbier registers corrected to $001b and $0021 repectively in first bullet on page 333, vector addresses corrected to $00d2 and $00d3. revision history mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 402 freescale semiconductor major changes between revisi on 2.0 and revision 1.0 the following table lists the major changes betw een the current revision of the mc68hc908az60a technical data book, rev 2.0, and the previous revision, rev 1.0. major changes between revisi on 1.0 and revision 0.0 the following table lists the major changes betw een the current revision of the mc68hc908az60a technical data book, rev 1.0, and the previous revision, rev 0.0. section affected description of change timer interface module b (timb) various changes for clarification. programmable interrupt timer (pit) timer interface module a (tima) section affected description of change general description highlighted that keyboard interrupt module only available in 64 qfp. corrected device name in figure 5 title. added adc supply and reference pins to pin descriptions. corrected text in numerous pin descriptions. added vdda and vssa pi ns to table 1-external pins summary. added table 2-clock signal naming conventions. added flash and ram to table 3-clock source summary. corrected part numbers in table 4-mc order numbers. memory map corrected type errors. corrected various addresses and regist er names in figure 1-memory map. corrected numerous register bit descriptions in figure 2-i/o data, status and control registers to match module sections. added additional status and control registers section and moved register descriptions accordingly. corrected bit descriptions to match module sections. added vector addresses and priority section and moved table 4-vector addresses accordingly. flash-1 and flash-2 both sections altered signi ficantly to better align module descriptions across groups within freescale using 0.5 tsmc/sst flash. numerous additions submitted by applications engineering fo r further clarification of functional operation. eeprom-1 and eeprom-2 both sections altered signi ficantly to better align module descriptions across groups within freescale using 0.5 tsmc/sst flash. numerous additions submitted by applications engineering fo r further clarification of functional operation. clock generator module (cgm) corrected clock signal names and associated timing parameters for consistency and to match signal naming conventions. additional textual description added to reaction time calculation subsection. configuration register 2 (config-2) corrected figure 1-configuration register reserved bit descriptions for consistency. revision history mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 403 monitor rom (mon) modified figure 1-monitor mode circuit based upon recommendations from applications engineering. correct text of note 1 to table 2-mode differences. corrected type errors. corrected text describing state of unprogrammed flash in security subsection. corrected figure 6-monitor mode entry timing. computer operating properly (cop) corrected state of copl bit in functional description subsection. timer interface module b (timb) corrected numerous type and grammatical errors. corrected numerous pin and regist er name errors within text. corrected references to timb overflow interrupts (removed "channel x" references as they are incorrect). programmable interrupt timer (pit) corrected type and grammatical errors. corrected pit overflow interrupt enab le bit acronym from pie to poie. keyboard module (kbd) corrected addresses of kbscr and kbier within text. timer interface module a (tima-6) corrected numerous type and grammatical errors. corrected numerous pin and regist er name errors within text. corrected references to tima overflow interrupts (removed "channel x" references as they are incorrect). corrected functional description of tof flag. electrical specifications corrected type errors. increased vhi specification in maximum ratings to vdd + 4.5v. corrected formula for average junction temperature in thermal characteristics. added column for typical vdd supply current values in 5.0 volt dc electrical characteristics. decreased lvi trip voltage specification to 3.80v and increased lvi recovery voltage to 4.49v in 5.0 volt dc electrical characteristics. increased vhi specification to minimu m of vdd + 3.0v and maximum of vdd + 4.5v in 5.0 volt dc electrical characteristics. added unit columns to all cgm specification tables and adjusted text accordingly. corrected operating voltage specific ation in cgm operating conditions. added typical specifications for ka cq and ktrk parameters in cgm acquisition/lock time information. split memory characteristics table into separate ram memory characteristics, eeprom memory characteristics and flash memory characteristics tables. added maximum specification for eeprom auto bit set for each of program and erase operation in eeprom memory characteristics. corrected notes section of flash memory characteristics. added note 3 to bdlc transmitter vpw symbol timings table. appendix a added text describing elimination of need for vhi on irq pin to program/erase flash block protect registers. added subsection highlighting change of monitor mode entry and cop disable voltage change. added subsection highlighting change in lvi trip and recovery voltage specifications. section affected description of change revision history mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 404 freescale semiconductor mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 405 glossary a ? see ?accumulator (a).? accumulator (a) ? an 8-bit general-purpose register in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode ? a mode of pll operation during start up before the pll locks on a frequency. also see "tracking mode." address bus ? the set of wires that the cpu or dma uses to read and write memory locations. addressing mode ? the way that the cpu determines the operand address for an instruction. the m68hc08 cpu has 16 addressing modes. alu ? see ?arithmetic logic unit (alu).? arithmetic logic unit (alu) ? the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous ? refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate ? the total number of bits transmitted per unit of time. bcd ? see ?binary-coded decimal (bcd).? binary ? relating to the base 2 number system. binary number system ? the base 2 number system, having two di gits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (bcd) ? a notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit ? a binary digit. a bit has a valu e of either logic 0 or logic 1. branch instruction ? an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module ? a module in the m68hc08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint ? a number written into the break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). break interrupt ? a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus ? a set of wires that transfers logic signals. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 406 freescale semiconductor bus clock ? the bus clock is derived from the cgmout output from the cgm. the bus clock frequency, f op , is equal to the frequency of the oscill ator output, cgmxclk, divided by four. byte ? a set of eight bits. c ? the carry/borrow bit in the condition code regi ster. the cpu08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). ccr ? see ?condition code register.? central processor unit (cpu) ? the primary functioning unit of any computer system. the cpu controls the execution of instructions. cgm ? see ?clock generator module (cgm).? clear ? to change a bit from logic 1 to logic 0; the opposite of set. clock ? a square wave signal used to synchronize events in a computer. clock generator module (cgm) ? a module in the m68hc08 fam ily. the cgm generates a base clock signal from which the system clocks are derived. th e cgm may include a crystal oscillator circuit and or phase-locked loop (pll) circuit. comparator ? a device that compares the magnitude of tw o inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (cop) ? a counter module in the m68hc08 family that resets the mcu if allowed to overflow. condition code register (ccr) ? an 8-bit register in the cpu08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit ? one bit of a register manipulated by software to control the operation of the module. control unit ? one of two major units of the cpu. the control unit contains logic functions that synchronize the machine and direct various operations. the control unit decodes instructions and generates the internal control signals that perfo rm the requested operations. the outputs of the control unit drive the execution uni t, which contains the arithmetic logic unit (alu), cpu registers, and bus interface. cop ? see "computer operating properly module (cop)." counter clock ? the input clock to the tim counter. this clock is the output of the tim prescaler. cpu ? see ?central processor unit (cpu).? cpu08 ? the central processor unit of the m68hc08 family. cpu clock ? the cpu clock is derived from the cgmo ut output from the cgm. the cpu clock frequency is equal to the frequency of the oscillator output, cgmxclk, divided by four. cpu cycles ? a cpu cycle is one period of the internal bu s clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. the length of time required to execute an instruction is measured in cpu clock cycles. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 407 cpu registers ? memory locations that are wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the information in these registers. the cpu registers in an m68hc08 are: ? a (8-bit accumulator) ? h:x (16-bit index register) ? sp (16-bit stack pointer) ? pc (16-bit program counter) ? ccr (condition code regist er containing the v, h, i, n, z, and c bits) csic ? customer-specified integrated circuit cycle time ? the period of the operating frequency: t cyc =1/f op . decimal number system ? base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) ? a m68hc08 family module th at can perform data transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma transfe rs are faster and more code-efficient than cpu interrupts. dma ? see "direct memory access module (dma)." dma service request ? a signal from a peripheral to the dm a module that enables the dma module to transfer data. duty cycle ? a ratio of the amount of time the signal is on vers us the time it is off. duty cycle is usually represented by a percentage. eeprom ? electrically erasable, programmable, read-onl y memory. a nonvolatile type of memory that can be electrically reprogrammed. eprom ? erasable, programmable, read-only memory. a nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception ? an event such as an interrupt or a rese t that stops the sequential execution of the instructions in the main program. external interrupt module (irq) ? a module in the m68hc08 fami ly with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch ? to copy data from a memory location into the accumulator. firmware ? instructions and data programmed into nonvolatile memory. free-running counter ? a device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission ? communication on a channel in wh ich data can be sent and received simultaneously. h ? the upper byte of the 16-bit index register (h:x) in the cpu08. h ? the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instruction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal ? base 16 numbering system that uses the digits 0 through 9 and the letters a through f. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 408 freescale semiconductor high byte ? the most significant eight bits of a word. illegal address ? an address not within the memory map illegal opcode ? a nonexistent opcode. i ? the interrupt mask bit in the condition code regist er of the cpu08. when i is set, all interrupts are disabled. index register (h:x) ? a 16-bit register in the cpu08. the upper byte of h:x is called h. the lower byte is called x. in the indexed addressing modes, the cpu uses the c ontents of h:x to determine the effective address of the operand. h:x can also serve as a temporary data storage location. input/output (i/o) ? input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions ? operations that a cpu can perform. inst ructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode and its associated operand(s) and instruction. interrupt ? a temporary break in the sequential execut ion of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request ? a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o ? see ?input/output (i/0).? irq ? see "external interrupt module (irq)." jitter ? short-term signal instability. latch ? a circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency ? the time lag between instruction completion and data movement. least significant bit (lsb) ? the rightmost digit of a binary number. logic 1 ? a voltage level approximately equal to the input power voltage (v dd ). logic 0 ? a voltage level approximately equal to the ground voltage (v ss ). low byte ? the least significant eight bits of a word. low voltage inhibit module (lvi) ? a module in the m68hc08 family that monitors power supply voltage. lvi ? see "low voltage inhibit module (lvi)." m68hc08 ? a freescale family of 8-bit mcus. mark/space ? the logic 1/logic 0 convention used in formatting data in serial communication. mask ? 1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option ? a optional microcontroller feature that the customer chooses to enable or disable. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 409 mask option register (mor) ? an eprom location containing bits that enable or disable certain mcu features. mcu ? microcontroller unit. see ?microcontroller.? memory location ? each m68hc08 memory location holds one byte of data and has a unique address. to store information in a memory location, the cp u places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the selected memory location places its data onto the data bus. memory map ? a pictorial representation of all memory locations in a computer system. microcontroller ? microcontroller unit (mcu). a complete computer system, including a cpu, memory, a clock oscillator, and input/output (i/o) on a single integrated circuit. modulo counter ? a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom ? a section of rom that can execute co mmands from a host computer for testing purposes. mor ? see "mask option register (mor)." most significant bit (msb) ? the leftmost digit of a binary number. multiplexer ? a device that can select one of a number of inputs and pass the logic level of that input on to the output. n ? the negative bit in the condition code register of the cpu08. the cpu sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble ? a set of four bits (half of a byte). object code ? the output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode ? a binary code that instructs the cpu to perform an operation. open-drain ? an output that has no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand ? data on which an operation is performed. us ually a statement consists of an operator and an operand. for example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator ? a circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. otprom ? one-time programmable read-only memory. a nonvolatile type of memory that cannot be reprogrammed. overflow ? a quantity that is too large to be contained in one byte or one word. page zero ? the first 256 bytes of memory (addresses $0000?$00ff). glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 410 freescale semiconductor parity ? an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expected to have an odd number of logic 1s. in an even parity system, every byte should have an even numbe r of logic 1s. in the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver c ounts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. pc ? see ?program counter (pc).? peripheral ? a circuit not under direct cpu control. phase-locked loop (pll) ? a oscillator circuit in which the freque ncy of the oscillator is synchronized to a reference signal. pll ? see "phase-locked loop (pll)." pointer ? pointer register. an index register is someti mes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity ? the two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, v dd and v ss . polling ? periodically reading a status bit to monitor the condition of a peripheral device. port ? a set of wires for communicating with off-chip devices. prescaler ? a circuit that generates an output signal relat ed to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program ? a set of computer instructions that caus e a computer to perform a desired operation or operations. program counter (pc) ? a 16-bit register in the cpu08. the pc register holds the address of the next instruction or operand that the cpu will use. pull ? an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup ? a transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width ? the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) ? controlled variation (modulation) of the pulse width of a signal with a constant frequency. push ? an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period ? the time required for one complete cycle of a pwm waveform. ram ? random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit ? a circuit consisting of capacitors and resistors having a defined time constant. read ? to copy the contents of a memory location to the accumulator. register ? a circuit that stores a group of bits. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 freescale semiconductor 411 reserved memory location ? a memory location that is used only in special factory test modes. writing to a reserved location has no effect. reading a reserved location returns an unpredictable value. reset ? to force a device to a known condition. rom ? read-only memory. a type of memory that can be read but cannot be changed (written). the contents of rom must be specified before manufacturing the mcu. sci ? see "serial communication interface module (sci)." serial ? pertaining to sequential transmission over a single line. serial communications interface module (sci) ? a module in the m68hc08 family that supports asynchronous communication. serial peripheral interface module (spi) ? a module in the m68hc08 family that supports synchronous communication. set ? to change a bit from logic 0 to logic 1; opposite of clear. shift register ? a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed ? a binary number notation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. the other sev en bits indicate the magnitude of the number. software ? instructions and data that control the operation of a microcontroller. software interrupt (swi) ? an instruction that causes an interrupt and its associated vector fetch. spi ? see "serial peripheral interface module (spi)." stack ? a portion of ram reserved for storage of cpu register contents and subroutine return addresses. stack pointer (sp) ? a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit ? a bit that signals the beginning of an asynchronous serial transmission. status bit ? a register bit that indicates the condition of a device. stop bit ? a bit that signals the end of an asynchronous serial transmission. subroutine ? a sequence of instructions to be used more than once in the course of a program. the last instruction in a subroutine is a return from subroutine (rts) instruction. at each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, the cpu returns to the main program where it left off. synchronous ? refers to logic circuits and operations that are synchronized by a common reference signal. tim ? see "timer interface module (tim)." timer interface module (tim) ? a module used to relate events in a system to a point in time. timer ? a module used to relate events in a system to a point in time. glossary mc68hc908az60a ? mc68hc908as60a ? mc68hc908as60e data sheet, rev. 6 412 freescale semiconductor toggle ? to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode ? mode of low-jitter pll operation during wh ich the pll is locked on a frequency. also see "acquisition mode." two?s complement ? a means of performing binary subtraction using addition techniques. the most significant bit of a two?s complement number indica tes the sign of the number (1 indicates negative). the two?s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered ? utilizes only one register for data; new data overwrites current data. unimplemented memory location ? a memory location that is not used. writing to an unimplemented location has no effect. reading an unimplemented loca tion returns an unpredictable value. executing an opcode at an unimplemented location causes an illegal address reset. v ?the overflow bit in the condition code register of the cpu08. the cpu08 sets the v bit when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable ? a value that changes during the course of program execution. vco ? see "voltage-controlled oscillator." vector ? a memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) ? a circuit that produces an osc illating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform ? a graphical representation in which the ampl itude of a wave is plotted against time. wired-or ? connection of circuit outputs so that if any output is high, the connection point is high. word ? a set of two bytes (16 bits). write ? the transfer of a byte of data from the cpu to a memory location. x ? the lower byte of the index register (h:x) in the cpu08. z ? the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. mc68hc908az60a rev. 6, 05/2006 |
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